Patents Assigned to Qimonda AG
  • Patent number: 9111609
    Abstract: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 18, 2015
    Assignees: International Business Machines Corporation, Qimonda AG
    Inventors: Thomas D. Happ, Alejandro G. Schrott
  • Patent number: 9064794
    Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: June 23, 2015
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd, Qimonda AG
    Inventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
  • Patent number: 8912654
    Abstract: An integrated circuit with a substrate with a lower and an upper surface is described. A via extends between the upper and the lower surface of the substrate. The via contains a conductive filling material that comprises carbon.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: December 16, 2014
    Assignee: Qimonda AG
    Inventors: Franz Kreupl, Harry Hedler
  • Patent number: 8879260
    Abstract: The memory module comprises a circuit board with a first and a second side, wherein memory chips are arranged at least on the first side. A longitudinally extending module heat conductor is arranged on the first side. The module heat conductor comprises a contact surface configured to contact a heat transfer system.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: November 4, 2014
    Assignee: Qimonda AG
    Inventors: Sven Kalms, Christian Weiss
  • Patent number: 8797811
    Abstract: A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: August 5, 2014
    Assignee: Qimonda AG
    Inventor: Jong-Hoon Oh
  • Patent number: 8779495
    Abstract: An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 15, 2014
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 8756393
    Abstract: Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write command when a write signal is applied to the write signal connection during an edge of the system clock signal.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 17, 2014
    Assignee: Qimonda AG
    Inventor: Kazimierz Szczypinski
  • Patent number: 8742387
    Abstract: An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: June 3, 2014
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Franz Kreupl, Jan Boris Philipp, Petra Majewski
  • Patent number: 8694726
    Abstract: A memory module system, a method for operating a memory module system, and an adapter card is disclosed. One embodiment provides last one memory buffer device, and a first plug mechanism for connecting the adapter card to a memory module system, and a second plug mechanism for connecting the adapter card to a memory module.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: April 8, 2014
    Assignee: Qimonda AG
    Inventors: Daniel Mysliwitz, Jens Niemax
  • Patent number: 8674999
    Abstract: An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 18, 2014
    Assignee: Qimonda AG
    Inventor: Thomas Hein
  • Publication number: 20140065787
    Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
    Type: Application
    Filed: November 7, 2013
    Publication date: March 6, 2014
    Applicants: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
  • Patent number: 8665629
    Abstract: An integrated circuit and method for manufacturing an integrated circuit are described. In one embodiment, the integrated circuit includes a memory cell that includes a resistivity changing memory element. The resistivity changing memory element is electrically coupled to a select transistor that includes a FinFET including a source, a drain, and a fin structure formed above a surface of a substrate between the source and the drain. The fin structure includes a channel area extending in a direction substantially parallel to the surface of the substrate, and a dielectric layer formed around at least a portion of the channel area such that an effective channel width of the select transistor depends at least in part on a height of the fin structure.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 4, 2014
    Assignees: Qimonda AG, Altis Semiconductor, SNC
    Inventors: Human Park, Ulrich Klostermann, Rainer Leuschner
  • Patent number: 8664657
    Abstract: A circuit is disclosed. The circuit includes at least one nanostructure and a carbon interconnect formed by a substantially carbon layer, wherein the nanostructure and the carbon interconnect are directly coupled to one another.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 4, 2014
    Assignee: Qimonda AG
    Inventors: Georg Duesberg, Franz Kreupl, Robert Seidel, Gernot Steinlesberger
  • Patent number: 8637844
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: January 28, 2014
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AG
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
  • Patent number: 8635393
    Abstract: The invention relates to a method for reading data from a semiconductor memory, said method comprising the following steps in this order: providing at least one first memory bank and at least one shadow memory bank which are each designed to store a multiplicity of binary data items, the same data as in the first memory bank being stored in the shadow memory bank; receiving a command for reading data which are to be read from the first memory bank; utilizing a state checking device of the semiconductor memory to check whether the first memory bank is in an open memory bank state, and, if the first memory bank is in the open memory bank state, reading the data which are to be read from the at least one shadow memory bank, and, if the first memory bank is not in the open memory bank state, reading the data which are to be read from the first memory bank, the open memory state being such a memory state of the memory bank which does not allow the data which are to be read to be read without previously closing an
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: January 21, 2014
    Assignee: Qimonda AG
    Inventors: Jean-Marc Dortu, Wolfgang Spirkl
  • Patent number: 8633053
    Abstract: A photovoltaic device is described. The photovoltaic device comprises an organic-based antireflection layer. A method of making a photovoltaic device is also described.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: January 21, 2014
    Assignee: Qimonda AG
    Inventors: Martin Detje, Iris Maege, Lars Voelkel
  • Patent number: 8631383
    Abstract: An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells being adapted to perform a substantially same functionality. Corresponding functional structures of the first and the second cell are electrically connected, at different locations inside the standard cells, to information carrying signal interconnection lines, wherein the functional structures are adapted to serve as an information carrying signal input or as an information carrying signal output.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 14, 2014
    Assignee: Qimonda AG
    Inventor: Michael Wagner
  • Patent number: 8629575
    Abstract: A description is given of a method for charge reversal of a circuit part of an integrated circuit from a first electrical potential to a second electrical potential of a first voltage network. In this case, the circuit part is connected to the first voltage network for charge reversal. Furthermore, the circuit part is connected to a second voltage network for charge reversal, said second voltage network providing a third electrical potential between the first and the second electrical potential. The circuit part is automatically isolated from the second voltage network before its electrical potential reaches the second electrical potential.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: January 14, 2014
    Assignee: Qimonda AG
    Inventors: Harald Roth, Helmut Schneider
  • Patent number: 8618600
    Abstract: Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 31, 2013
    Assignee: Qimonda AG
    Inventor: Stafan Slesazeck
  • Patent number: 8606982
    Abstract: Embodiments of the invention are related to methods, systems, and articles of manufacture for transferring data between two devices using an interconnect bus. On each conductive line of the bus, a bit representing a first logic state is transferred if a current bit is the same as an immediately previously transmitted bit. If the current bit is different from the immediately previously transmitted bit, then a bit representing a second logic state is transferred.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: December 10, 2013
    Assignee: Qimonda AG
    Inventors: Michael Maldei, Petra Stumm