Patents Assigned to Qimonda AG
  • CIRCUIT
    Publication number: 20120198265
    Abstract: An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.
    Type: Application
    Filed: April 10, 2012
    Publication date: August 2, 2012
    Applicant: QIMONDA AG
    Inventor: Thomas Hein
  • Methods for elimination or reduction of oxide and/or soot deposition in carbon containing layers
    Patent number: 8216639
    Abstract: One embodiment of the present invention provides a method for the deposition of a Carbon containing layer on a Silicon surface wherein a (i) substantially Silicon-oxide-free or reduced oxide interface results between Silicon and the Carbon containing layer during the deposition. In another embodiment, the present invention provides a method for deposition of a Carbon containing layer wherein the deposition process is substantially soot (particle)-free or reduction of soot.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: July 10, 2012
    Assignee: Qimonda AG
    Inventors: Maik Liebau, Franz Kreupl, Georg Duesberg, Eugen Unger
  • Circuit
    Patent number: 8207976
    Abstract: An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: June 26, 2012
    Assignee: Qimonda AG
    Inventor: Thomas Hein
  • Resistive memory cell accessed using two bit lines
    Patent number: 8208294
    Abstract: An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: June 26, 2012
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Information transmission and reception
    Patent number: 8201071
    Abstract: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: June 12, 2012
    Assignee: Qimonda AG
    Inventors: Thomas Hein, Rex Kho, Aaron John Nygren
  • Memory module and method for operating a memory module
    Patent number: 8199521
    Abstract: A memory module includes an electronic printed circuit board with at least one contact strip, a plurality of integrated memory components, at least one first and one second buffer component, and a number of conductor tracks, which proceed from the contact strip and which are arranged on or in the printed circuit board. The conductor tracks include data lines, control lines and address lines. The conductor tracks lead from the contact strip to the buffer components or to one of the buffer components. The printed circuit board has conductor tracks that are interposed between the first buffer component and the second buffer component and that lead from the first buffer component to the second buffer component.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: June 12, 2012
    Assignee: Qimonda AG
    Inventor: Simon Muff
  • Integrated circuit including electrode having recessed portion
    Patent number: 8189372
    Abstract: An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: May 29, 2012
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AG
    Inventors: Matthew Breitwisch, Shihhung Chen, Thomas Happ, Eric Joseph
  • Phase change random access memory device with transistor, and method for fabricating a memory device
    Patent number: 8188569
    Abstract: The invention relates to a memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”). In one disclosed method, a nanowire of non-conducting material is formed serving as a mould for producing a nanotube of conducting material. A volume of switching active material is deposited on top of the nanotube, so that the ring-shaped front face of the nanotube couples to the switching active material and thus forms a bottom electrode contact.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: May 29, 2012
    Assignee: Qimonda AG
    Inventor: Harald Seidl
  • Memory device including an electrode having an outer portion with greater resistivity
    Patent number: 8189374
    Abstract: A memory cell includes a first electrode having a first region and a second region, a second electrode and a phase change material. The phase change material is interposed between the first electrode and the second electrode with the first region of the first electrode arranged closer to the phase change material than the second region. The first region of the first electrode includes an inner portion laterally surrounded by an outer portion. The outer portion has a greater resistivity than the inner portion. The second region of the first electrode has the same resistivity as the inner portion of the first region.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: May 29, 2012
    Assignee: Qimonda AG
    Inventor: Shoaib Zaidi
  • Methods and apparatus for operating a digital communications interface
    Patent number: 8189726
    Abstract: Embodiments of the invention relate to integrated circuits comprising inputs for receiving an input signal and a plurality of clock signals having a predetermined phase relationship. The integrated circuit may include a plurality of track-and-hold devices and a plurality of slicer devices. Signal outputs of two track-and-hold devices may be coupled to signal inputs of one slicer device, one of the two track-and-hold devices and the slicer device being coupled to a first input configured to receive a first clock signal and the other track-and-hold device being coupled to a second input being configured to receive a second clock signal.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: May 29, 2012
    Assignee: Qimonda AG
    Inventors: Franz Weiss, Daniel Kehrer
  • MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS
    Publication number: 20120126301
    Abstract: One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 24, 2012
    Applicant: Qimonda AG
    Inventors: Gerhard Kunkel, Peter Baars
  • Memory circuit having memory chips parallel connected to ports and corresponding production method
    Patent number: 8183676
    Abstract: A memory circuit includes multiple memory chips configured to store data and disposed in at least one stack. The memory circuit includes multiple ports configured to receive and transmit control signals and data to and from the memory chips and to supply energy to the memory circuit. The memory circuit includes a housing accommodating the multiple memory chips and the multiple ports.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: May 22, 2012
    Assignee: Qimonda AG
    Inventors: Simon Muff, Hermann Ruckerbauer
  • Memory system and method for using a memory system with virtual address translation capabilities
    Patent number: 8185716
    Abstract: A memory system comprises a first memory having associated therewith a first local memory access controller configured to access the first local memory using physical memory addresses and a second memory having associated therewith a second local memory access controller configured to access the second local memory using physical memory addresses. A global controller coupled to the first and second local controllers is configured to communicate virtual memory addresses to the first and second local memory controllers.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: May 22, 2012
    Assignee: Qimonda AG
    Inventors: Maurizio Skerlj, Paolo Ienne Lopez
  • Integrated circuit, resistivity changing memory device, memory module, and method of fabricating an integrated circuit
    Patent number: 8178379
    Abstract: According to one embodiment of the present invention, a memory device includes a composite structure including a resistivity changing layer and an electrode layer being arranged on or above the resistivity changing layer. The resistivity changing memory device further includes a protection layer being arranged on or above the composite structure, the protection layer protecting the electrode layer against electromagnetic waves.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: May 15, 2012
    Assignees: Qimonda AG, ALTIS Semiconductor, SNC
    Inventors: Philippe Blanchard, Gill Yong Lee
  • Integrated circuits having a contact structure having an elongate structure and methods for manufacturing the same
    Patent number: 8178927
    Abstract: In an embodiment, an integrated circuit is provided. The integrated circuit may include an active area extending along a first direction corresponding to a current flow direction through the active area, a contact structure having an elongate structure. The contact structure may be electrically coupled with the active area. Furthermore, the contact structure may be arranged such that the length direction of the contact structure forms a non-zero angle with the first direction of the active area.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: May 15, 2012
    Assignee: Qimonda AG
    Inventor: Lars Bach
  • Memory-Module Controller, Memory Controller and Corresponding Memory Arrangement, and Also Method for Error Correction
    Publication number: 20120110414
    Abstract: A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.
    Type: Application
    Filed: November 2, 2011
    Publication date: May 3, 2012
    Applicant: QIMONDA AG
    Inventors: Torsten Hinz, Gerhard Risse
  • System for electronic components mounted on a circuit board
    Patent number: 8164915
    Abstract: A system for electronic components mounted on a circuit board is disclosed. One embodiment provides placing an elastic, anisotropically conductive material on top of a printed circuit board. An electronic component is placed over the elastic, anisotropically conductive material, fixing the electronic component on the printed circuit board.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: April 24, 2012
    Assignee: Qimonda AG
    Inventor: Jens Niemax
  • Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed
    Patent number: 8161219
    Abstract: Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: April 17, 2012
    Assignee: Qimonda AG
    Inventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gärtner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker
  • Circuits and methods for error coding data blocks
    Patent number: 8161344
    Abstract: A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to create the error coding data block in accordance with a second error coding; the error coding data block for the first data block being created optionally by the first or second error coding paths, as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: April 17, 2012
    Assignee: Qimonda AG
    Inventor: Aaron Nygren
  • Integrated circuit device having openings in a layered structure
    Patent number: 8158485
    Abstract: An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: April 17, 2012
    Assignee: Qimonda AG
    Inventors: Daniel Köhler, Manfred Engelhardt, Peter Baars, Hans-Peter Sperlich