Patents Assigned to Qimonda AG
  • Integrated circuit and method for producing the same
    Patent number: 8143714
    Abstract: An integrated circuit provides a carrier substrate, a wiring level above a carrier substrate, wherein the wiring level comprises a first conductor track composed of a first conductive material and a second conductor track composed of the first conductive material, an insulating layer above the wiring level, wherein the insulating layer comprises a first opening in a region of the first conductor track of the wiring level and a second opening in a region of the second conductor track of the wiring level and a contact bridge composed of a second conductive material, wherein the contact bridge is connected to the first conductor track in a region of the first opening and is connected to the second conductor track in a region of the second opening.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: March 27, 2012
    Assignee: Qimonda AG
    Inventors: Minka Gospodinova-Daltcheva, Ingo Wennemuth, Hayri Burak Goekgoez
  • Multi-chip package with interconnected stacked chips
    Patent number: 8138610
    Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: March 20, 2012
    Assignee: Qimonda AG
    Inventors: Jong Hoon Oh, Klaus Hummler, Oliver Kiehl, Josef Schnell, Wayne Frederick Ellis, Jung Pil Kim, Lee Ward Collins, Octavian Beldiman
  • Interconnect structure for semiconductor devices
    Patent number: 8138538
    Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: March 20, 2012
    Assignee: Qimonda AG
    Inventors: Hans-Peter Moll, Gouri Sankar Kar, Martin Popp, Lars Heineck, Peter Lahnor, Arnd Scholz, Stefan Jakschik, Wolfgang Roesner, Gerhard Enders, Werner Graf, Peter Baars, Klaus Muemmler, Bernd Hintze, Andrei Josiek
  • Phase change memory cell with MOSFET driven bipolar access device
    Patent number: 8130537
    Abstract: Embodiments are directed to memory devices comprising a bipolar junction transistor having an emitter, a base and a collector; a first side of a resistance changing memory element coupled to the emitter of the bipolar junction transistor; and a MOSFET coupled to the base of the bipolar junction transistor.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: March 6, 2012
    Assignee: Qimonda AG
    Inventor: Rolf Weis
  • Method and device for transmitting outgoing useful signals and an outgoing clock signal
    Patent number: 8125812
    Abstract: Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: February 28, 2012
    Assignee: Qimonda AG
    Inventors: Martin Streibl, Peter Gregorius, Ralf Schledz
  • Array of low resistive vertical diodes and method of production
    Patent number: 8125006
    Abstract: An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 28, 2012
    Assignee: Qimonda AG
    Inventors: Ulrike Gruening-von Schwerin, Peter Baars, Klaus Muemmler, Stefan Tegen, Thomas Happ
  • Electrical through contact
    Patent number: 8124521
    Abstract: A method of fabricating an electrical contact through a through hole in a substrate, wherein the through hole is at least in part filled with a liquid conductive material and the solidified liquid conductive material provides an electrical contact through the through hole.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: February 28, 2012
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Roland Irsigler, Volker Lehmann, Judith Lehmann, legal representative, Thorsten Meyer, Octavio Trovarelli
  • Integrated circuit and method
    Patent number: 8120186
    Abstract: An integrated circuit and method of fabricating an integrated circuit. One embodiment includes a circuit chip, a contact pad, and a projecting top contact. A signal line couples the contact pad to the projecting top contact, the contact pad, the projecting top contact. The signal line is arranged on a top face of the circuit chip. A substrate and a lower contact pad, the lower contact pad is arranged on a bottom face of the substrate and the circuit chip is arranged on a top face of the substrate. A bottom face of the circuit chip is facing the top face of the substrate. A connection couples the contact pad on the circuit chip to the lower contact pad.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: February 21, 2012
    Assignee: Qimonda AG
    Inventor: Kimyung Yoon
  • Integrated circuit including an ECC error counter
    Patent number: 8122320
    Abstract: An integrated circuit includes a memory array and an error correction code (ECC) circuit configured to provide a first signal indicating whether data read from the memory array has been corrected by the ECC circuit. The integrated circuit includes a mimic circuit configured to provide a second signal indicating whether the first signal is valid and a counter configured to increment in response to the second signal indicating the first signal is valid and the first signal indicating an error.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: February 21, 2012
    Assignee: Qimonda AG
    Inventors: Khaled Fekih-Romdhane, Peter Chlumecky
  • Multi-bank memory device method and apparatus
    Patent number: 8120985
    Abstract: In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the semiconductor substrate. Each memory bank of the second set is split into a plurality of memory bank segments physically separated from each other and from the first set of memory banks. Each memory bank segment is arranged adjacent to, and occupies less area than, one of the memory banks of the first set.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: February 21, 2012
    Assignee: Qimonda AG
    Inventors: Christopher Kunce, Benjamin Heilmann, Alan Daniel
  • Multi-die memory, apparatus and multi-die memory stack
    Patent number: 8120958
    Abstract: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.
    Type: Grant
    Filed: December 24, 2007
    Date of Patent: February 21, 2012
    Assignee: Qimonda AG
    Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
  • Integrated circuit comprising conductive lines and contact structures and method of manufacturing an integrated circuit
    Patent number: 8120182
    Abstract: An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: February 21, 2012
    Assignee: Qimonda AG
    Inventors: Andreas Thies, Sirko Kramp, Helmut Schneider, Rainer Florian Schnabel
  • Integrated circuit
    Patent number: 8116157
    Abstract: An integrated circuit is disclosed. One embodiment provides a sense amplifier; a first bit line; a second bit line. A first switch is configured to connect/disconnect the first bit line to/from the sense amplifier. A second switch is configured to connect/disconnect the second bit line to/from the sense amplifier independently from the first switch.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: February 14, 2012
    Assignee: Qimonda AG
    Inventors: Michael Bruennert, Harald Roth
  • Integrated circuit having a material structured by a projection
    Patent number: 8115277
    Abstract: A method of making an integrated circuit including structuring a material. The method includes providing an arrangement of three-dimensional bodies. The material is arranged between the bodies and structured directed radiation. The projection pattern of the three-dimensional bodies is transferred into the material. The structured material connects at least two of the three-dimensional bodies.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 14, 2012
    Assignee: Qimonda AG
    Inventor: Johannes Von Kluge
  • Apparatus and method for generating a transmit signal and apparatus and method for extracting an original message from a received signal
    Patent number: 8117526
    Abstract: A method for extracting an original message from a received signal including data bits representing the original message or an inverted version thereof, an indicator indicating whether the data bits represent the original message or the inverted version thereof, and a check information which depends on the data bits and the indicator, the method including determining a check information based on the received data bits and the received indicator, comparing the determined check information with the received check information and extracting the original message based on the result of the comparison.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: February 14, 2012
    Assignee: Qimonda AG
    Inventor: Maurizio Skerlj
  • SEMICONDUCTOR PACKAGE AND METHOD OF ATTACHING SEMICONDUCTOR DIES TO SUBSTRATES
    Publication number: 20120034738
    Abstract: A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds.
    Type: Application
    Filed: October 20, 2011
    Publication date: February 9, 2012
    Applicants: QIMONDA AG, UNITED TEST AND ASSEMBLY CENTER, LTD.
    Inventors: Denver Paul C. CASTILLO, Bryan Soon Hua TAN, Rodel MANALAC, Kian Teng ENG, Pang Hup ONG, Soo Pin CHOW, Wolfgang Johannes HETZEL, Werner Josef REISS, Florian AMMER
  • Integrated circuit
    Patent number: 8106686
    Abstract: An integrated circuit includes an input terminal for applying an input signal, a further input terminal for applying a further input signal having a level differing from the level of the initial input signal, an output terminal for providing an output signal, a switching unit having a controllable switch, which is arranged between the input terminal and the output terminal, and a further switching unit, which is arranged between the further input terminal and the output terminal. The integrated circuit is operated in a first and subsequent second operating state. The controllable switch of the switching unit is controlled to be conductive in the first and second operating state. In the first operating state, the output signal is provided in dependence on the level of the input signal, and in the second operating state in dependence on the level of the second input signal.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: January 31, 2012
    Assignee: Qimonda AG
    Inventors: Harald Roth, Helmut Schneider
  • Semiconductor memory chip and memory system
    Patent number: 8108643
    Abstract: In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: January 31, 2012
    Assignee: Qimonda AG
    Inventors: Paul Wallner, Peter Gregorius
  • Method and apparatus for fast and local anneal of anti-ferromagnetic (AF) exchange-biased magnetic stacks
    Patent number: 8105445
    Abstract: A method (and structure) of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 31, 2012
    Assignees: International Business Machines Corporation, Qimonda AG
    Inventors: Ulrich Karl Klostermann, Wolfgang Raberg, Philip Trouilloud
  • Semiconductor memory module, electronic apparatus and method for operating thereof
    Patent number: RE43162
    Abstract: A semiconductor memory module (1) includes a circuit substrate (2), a first (100), a second (200), a third (300) and a fourth (400) rank of memory chips (3), a first register (10) and a second register (20). The first register (10) and the second register (20) each comprise a first input (11, 21) for receiving a respective chip select signal (CS0, CS2), a second input (12, 22) for receiving a respective other chip select signal (CS1, CS3) at least one third input (13, 23) for receiving command/address signals (CA), and at least one third output (16, 26).
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: February 7, 2012
    Assignee: Qimonda AG
    Inventor: Siva RaghuRam