Patents Assigned to Qimonda AG
  • Integrated circuit, and method for transferring data
    Patent number: 7903480
    Abstract: An integrated circuit and a method for transferring data is provided. One embodiment provides a method for transferring data in an integrated circuit. The method includes driving a first line in accordance with data to be transferred. The data is transmitted from the first line to a second line based on a capacitive coupling.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: March 8, 2011
    Assignee: Qimonda AG
    Inventors: Konrad Seidel, Reinhard Ronneberger, Mario Wallisch
  • Method for fabrication of single crystal diodes for resistive memories
    Patent number: 7902051
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 8, 2011
    Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
  • Memory module system and method for operating a memory module
    Patent number: 7899984
    Abstract: A memory module system, a memory module, a buffer device, a memory module printed circuit board, and to a method for operating a memory module is disclosed. In one embodiment, the memory module system includes at least a first, a second, and a third memory module. The first memory module is connected with the second memory module via a first connection and with the third memory module via a second connection, and is designed and equipped such that data, address, and/or control signals received by the first memory module are transmitted to the second memory module via the first connection and to the third memory module via the second connection.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: March 1, 2011
    Assignee: Qimonda AG
    Inventor: Gerhard Risse
  • Integrated circuit having memory cells and method of manufacture
    Patent number: 7898006
    Abstract: An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: March 1, 2011
    Assignee: Qimonda AG
    Inventor: Ulrike Gruening-von Schwerin
  • Method to prevent overreset
    Patent number: 7898847
    Abstract: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: March 1, 2011
    Assignee: Qimonda AG
    Inventor: Jan Boris Philipp
  • Multi-mode bus inversion method and apparatus
    Patent number: 7899961
    Abstract: In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: March 1, 2011
    Assignee: Qimonda AG
    Inventor: Rom-Shen Kao
  • Method and apparatus for performing internal hidden refreshes while latching read/write commands, address and data information for later operation
    Patent number: 7894290
    Abstract: A method of operating a system including a memory device. The method includes, upon receiving a request for an internal hidden refresh for the memory device, latching external command, address, and data information for the memory device. The method further includes placing the memory device in a standby state and during the standby state, performing the internal hidden refresh. The method further includes, after performing the internal hidden refresh, placing the memory device in a state corresponding to the latched external command, address, and data information for the memory device.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: February 22, 2011
    Assignee: Qimonda AG
    Inventor: Jochen Hoffmann
  • Method and apparatus for reducing charge trapping in high-k dielectric material
    Patent number: 7894240
    Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: February 22, 2011
    Assignee: Qimonda AG
    Inventors: Michael Beck, Martin Kerber, Peter Lahnor, Roland Thewes
  • Integrated circuit, memory module, and method of manufacturing an integrated circuit
    Patent number: 7893511
    Abstract: An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: February 22, 2011
    Assignee: Qimonda AG
    Inventors: Manfred Ruehrig, Ulrich Klostermann, Michael Vieth
  • Carbon filament memory and fabrication method
    Patent number: 7894253
    Abstract: An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive channel includes the first carbon material.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 22, 2011
    Assignee: Qimonda AG
    Inventors: Franz Kreupl, Michael Kund, Klaus-Dieter Ufert
  • Integrated circuit with conductive structures
    Patent number: 7893519
    Abstract: An integrated circuit includes an array of transistors and a number of wordlines, where individual ones of the wordlines are coupled to a number of the transistors in the array. Conductive structures that are insulated from the wordlines are disposed in a layer beneath the wordlines and are arranged between the transistors.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: February 22, 2011
    Assignee: Qimonda AG
    Inventor: Franz Hofmann
  • Integrated circuit including selectable address and data multiplexing mode
    Patent number: 7894283
    Abstract: An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 22, 2011
    Assignee: Qimonda AG
    Inventors: Margaret Freebern, Wolfgang Hokenmaier, Donald Labrecque, Steffen Loeffler, Ralf Klein
  • Memory including periphery circuitry to support a portion or all of the multiple banks of memory cells
    Patent number: 7889589
    Abstract: A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventors: Steffen Loeffler, Wolfgang Hokenmaier
  • Controlling an analog signal in an integrated circuit
    Patent number: 7888948
    Abstract: A method of controlling an analog signal in an integrated circuit includes generating a first control signal having a first predetermined duration within the integrated circuit. The first control signal is configured to cause the analog signal to have a first signal level. The first signal level is compared to a level of a target signal. A second control signal is generated within the integrated circuit based on a result of the comparison. The second control signal is configured to cause the analog signal to have a second signal level. The second control signal has a second predetermined duration that is different than the first predetermined duration.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventor: Andreas Jakobs
  • Integrated circuit including quench devices
    Patent number: 7889536
    Abstract: An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Method of making an integrated circuit including structuring a material
    Patent number: 7888230
    Abstract: A method of making an integrated circuit including structuring a material. The method includes providing an arrangement of three-dimensional bodies. The material is arranged between the bodies and structured directed radiation. The projection pattern of the three-dimensional bodies is transferred into the material. The structured material connects at least two of the three-dimensional bodies.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventor: Johannes von Kluge
  • Integrated circuit including memory cell having cup-shaped electrode interface
    Patent number: 7888665
    Abstract: An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated circuit includes a second electrode coupled to the resistance changing material.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Stacking Technique for Circuit Devices
    Publication number: 20110034045
    Abstract: Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device.
    Type: Application
    Filed: August 6, 2009
    Publication date: February 10, 2011
    Applicant: QIMONDA AG
    Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
  • Semiconductor component with improved contact pad and method for forming the same
    Patent number: 7884488
    Abstract: A structure and method of forming low cost bond pads is described. In one embodiment, the invention includes depositing an insulating layer over a last metal line of a substrate and forming an opening in the insulating layer. A colloid is printed over the insulating layer and fills the opening in the insulating layer. A conductive via and bond pads are formed by heating the colloid.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: February 8, 2011
    Assignee: Qimonda AG
    Inventor: Harry Hedler
  • Method and apparatus for synchronizing memory enabled systems with master-slave architecture
    Patent number: 7882324
    Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 1, 2011
    Assignee: Qimonda AG
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins