Patents Assigned to Qimonda AG
  • Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer
    Patent number: 7880212
    Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: February 1, 2011
    Assignee: Qimonda AG
    Inventors: Bernd Hintze, Henry Bernhardt, Frank Bernhardt
  • Integrated circuit including a capacitor and method
    Patent number: 7880269
    Abstract: An integrated circuit including a capacitor and a method of fabricating an integrated circuit. The capacitor has a first electrode. A plurality of conductive lines is separated from each other and is configured to be held at a potential being the same for all conductive lines. A second electrode encloses individual ones of the conductive lines at a top side and at least one lateral side and is separated from the first electrode by a dielectric layer. The second electrode includes a polycrystalline semiconductor material, a metal or a metal-semiconductor compound.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: February 1, 2011
    Assignee: Qimonda AG
    Inventors: Frank Heinrichsdorff, Steffen Meyer, Jens Schmidt
  • Method of preparing a coating solution and a corresponding use of the coating solution for coating a substrate
    Patent number: 7879395
    Abstract: A method of preparing a coating solution, comprising the steps of providing a first solution comprising a lower alcohol; a polyethylene glycol; a complexing agent; and water; providing a second solution comprising a higher alcohol; and at least one metal alkoxide, wherein the metal in said at least one metal alkoxide is selected from the group consisting of zirconium, aluminium, titanium, tantalum and yttrium; forming a sol-gel solution by mixing said first and second solutions and thereby hydrolyzing said at least one metal alkoxide to a metal oxide and an alcohol; forming a concentrated solution by removing said lower alcohol and the alcohol resulting from the hydrolysis of said at least one metal alkoxide; and forming a coating solution by adding a medium alcohol to said concentrated solution.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: February 1, 2011
    Assignee: Qimonda AG
    Inventors: Andreas Klipp, Stephan Wege, Tobias Mayer-Uhma, Cornelia Klein, Alexander Michaelis, Falko Schlenkrich
  • Integrated circuit including an insulating structure below a source/drain region and method
    Patent number: 7880210
    Abstract: An integrated circuit including an insulating structure below a source/drain region and a method. One embodiment includes a memory cell with an access transistor and a storage element. A first source/drain region of the access transistor is electrically coupled to the storage element. A first insulating structure is disposed between the first source/drain region and a first portion of a semiconductor substrate, the first portion being arranged below the first source/drain region. A channel region of the access transistor is formed between the first and a second source/drain region of the access transistor in an active area being electrically coupled to the first portion of the semiconductor substrate.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: February 1, 2011
    Assignee: Qimonda AG
    Inventor: Dongping Wu
  • Memory using tunneling field effect transistors
    Patent number: 7880160
    Abstract: A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: February 1, 2011
    Assignee: Qimonda AG
    Inventor: Thomas Nirschl
  • Arrangement of stacked integrated circuit dice having a direct electrical connection
    Patent number: 7880309
    Abstract: An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is stacked onto the first die such that the first electrical coupling site is at least partially exposed, wherein the first electrical coupling site and the second electrical coupling site are directly electrically connected, and a third die arranged above the first die and the second die such that a recess is formed, wherein one of the first electrical coupling sites is arranged in the recess.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: February 1, 2011
    Assignee: Qimonda AG
    Inventor: Camillo Pilla
  • Integrated circuit for programming a memory cell
    Patent number: 7876606
    Abstract: An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Memory device
    Patent number: 7875985
    Abstract: A memory device comprising at least one memory stack of stacked memory dies which are staggered with respect to each other, each stacked memory die of said memory stack comprising along its edge die pads for bonding said stacked memory die to substrate pads of said memory device connectable to a control circuit, wherein each die pad of a stacked memory die which connects said memory die individually to said control circuit comprises an increased distance (di) in comparison to die pads of said stacked memory die which connect said stacked memory die in parallel with corresponding die pads of other stacked memory dies of said memory stack to said control circuit.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Dietmar Hiller, Roberto Dossi, Andreas Knoblauch
  • Apparatus and method for determining a memory state of a resistive n-level memory cell and memory device
    Patent number: 7876598
    Abstract: A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode is compared to a reference voltage to obtain a comparison signal. The comparison signal is sampled at, at least, (n?1) time instants during the charge or discharge of the read capacity to obtain sampling values. The memory state of the memory cell can be determined based upon the sampling values.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Peter Schroegmeier, Stefan Dietrich
  • Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs
    Patent number: 7877649
    Abstract: An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.
    Type: Grant
    Filed: November 2, 2007
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Joerg Kliewer, Manfred Proell, Stephan Schroeder, Georg Eggers, Wolfgang Ruf, Hermann Hass
  • Integrated circuit including a first gate stack and a second gate stack and a method of manufacturing
    Patent number: 7875516
    Abstract: An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Roman Knoefler, Michael Specht, Josef Willer
  • Integrated circuit including a memory fabricated using self-aligned processing
    Patent number: 7875492
    Abstract: An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Ulrike Gruening-von Schwerin, Thomas Happ
  • Multi-chip module
    Patent number: 7872350
    Abstract: A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: January 18, 2011
    Assignee: Qimonda AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Stefan Landau, Erwin Huber
  • Integrated circuit with bit lines positioned in different planes
    Patent number: 7872902
    Abstract: An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: January 18, 2011
    Assignee: Qimonda AG
    Inventors: Joerg Volrath, Marcin Gnat
  • Method of making transistor gates with controlled work function
    Patent number: 7871943
    Abstract: Embodiments of the invention provide methods for making an integrated circuit comprising providing a substrate, forming a structured layer stack on the substrate comprising a dielectric layer located on the substrate and an oxide-free metallic layer located on the dielectric layer, wherein the metallic layer comprising a transition metal. The method further comprises oxidizing the metallic layer, thereby increasing a work function of the metallic layer. Moreover, a substrate for making an integrated circuit is described.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: January 18, 2011
    Assignee: Qimonda AG
    Inventors: Tim Boescke, Tobias Mono
  • System and method for packaged memory
    Patent number: 7872936
    Abstract: In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: January 18, 2011
    Assignee: Qimonda AG
    Inventor: Dennis Blankenship
  • Multi-component module fly-by output alignment arrangement and method
    Patent number: 7873857
    Abstract: A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the components are programmed to delay outputting data by a corresponding amount of time. In one embodiment, the one or more components are programmed such that all of the components output data at substantially the same time when they respond to a control signal. This is particularly useful for multi-component modules that are configured to respond to control signals in a so-called fly-by (or other) configuration that results in the control signal arriving at the components at different times causing the components to react to the control signal at different times.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: January 18, 2011
    Assignee: Qimonda AG
    Inventors: Ronald Baker, George Alexander
  • Integrated circuit with an active area line having at least one form-supporting element and corresponding method of making an integrated circuit
    Patent number: 7868415
    Abstract: An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: January 11, 2011
    Assignee: Qimonda AG
    Inventors: Josef Willer, Michael Specht, Christoph Friederich, Doris Keitel-Schulz
  • Integrated circuit including diode memory cells
    Patent number: 7869257
    Abstract: The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: January 11, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Method for manufacturing a wafer level package
    Patent number: 7867817
    Abstract: A method for manufacturing a wafer level package of an integrated circuit element for direct attachment to a wiring board is disclosed. An integrated circuit element includes input/output pads located on an active side. A non-conductive support structure is formed on the active side of the integrated circuit element in an area that is free from input/output pads. A conductive path is formed upon the support structure and a non-conductive coating is formed on over the active side of the integrated circuit element such that a surface is formed which leaves interface pads accessible.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: January 11, 2011
    Assignee: Qimonda AG
    Inventors: Stephan Dobritz, Harry Hedler, Henning Mieth