Patents Assigned to Qimonda North America Corp.
  • Publication number: 20120134204
    Abstract: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.
    Type: Application
    Filed: February 2, 2012
    Publication date: May 31, 2012
    Applicants: QIMONDA NORTH AMERICA CORP., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas D. Happ, Alejandro G. Schrott
  • Patent number: 8138028
    Abstract: A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: March 20, 2012
    Assignees: Macronix International Co., Ltd, International Business Machines Corporation, Qimonda North America Corp.
    Inventors: Hsiang Lan Lung, Chieh Fang Chen, Yi Chou Chen, Shih Hung Chen, Chung Hon Lam, Eric Andrew Joseph, Alejandro Gabriel Schrott, Matthew J. Breitwisch, Geoffrey William Burr, Thomas D. Happ, Jan Boris Philipp
  • Patent number: 8124950
    Abstract: A memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: February 28, 2012
    Assignees: International Business Machines Corporation, Qimonda North America Corp.
    Inventors: Thomas D. Happ, Alejandro G. Schrott
  • Patent number: 7977987
    Abstract: Embodiment of the present invention relate to a method for receiving a first signal, determining a first characteristic of the first signal, the characteristic being a time based characteristic, receiving a second signal and processing the second signal through a predetermined range of delay elements, an initial minimum number of delay elements in the predetermined range being adjustable, the processed second signal having a second characteristic substantially corresponding to the first characteristic of the first signal.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: July 12, 2011
    Assignee: Qimonda North America Corp
    Inventor: Josh Osborne
  • Patent number: 7932507
    Abstract: A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: April 26, 2011
    Assignees: International Business Machines Corporation, Qimonda North America Corp., Macronix International Co., Ltd.
    Inventors: Chieh-Fang Chen, Shih Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
  • Patent number: 7886122
    Abstract: Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock signal may be less than the frequency of the second clock signal. The method further includes performing two or more data access operations using the second clock signal. One of the two or more data access operations may include a read operation and one of the two or more data access operations may include a write operation. The method also includes performing a command processing operation using the first clock signal.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: February 8, 2011
    Assignee: Qimonda North America Corp.
    Inventor: Jong-Hoon Oh
  • Patent number: 7872931
    Abstract: An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: January 18, 2011
    Assignee: Qimonda North America Corp.
    Inventor: Khaled Fekih-Romdhane
  • Patent number: 7863610
    Abstract: An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: January 4, 2011
    Assignees: Qimonda North America Corp., International Business Machines Corporation
    Inventors: Bipin Rajendran, Shoaib Hasan.Zaidi
  • Publication number: 20100321990
    Abstract: A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 23, 2010
    Applicant: QIMONDA NORTH AMERICA CORP.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20100323493
    Abstract: An integrated circuit is fabricated by providing a preprocessed wafer including a first electrode, depositing a dielectric material over the preprocessed wafer, etching an opening in the dielectric material to expose a portion of the first electrode and depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode. The first resistivity changing material is planarized to expose the etched dielectric material. A second resistivity changing material is deposited over the etched dielectric material and the first resistivity changing material, and an electrode material is deposited over the second resistivity changing material.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 23, 2010
    Applicant: QIMONDA NORTH AMERICA CORP.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Publication number: 20100306605
    Abstract: A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 2, 2010
    Applicant: Qimonda North America Corp.
    Inventors: KoonHee Lee, Ryan Patterson, Hoon Ryu, Klaus Nierle
  • Patent number: 7822910
    Abstract: Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: October 26, 2010
    Assignee: Qimonda North America Corp.
    Inventor: Rom-Shen Kao
  • Patent number: 7812333
    Abstract: An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode coupled to the second resistivity changing material. A cross-sectional width of the first resistivity changing material is less than a cross-sectional width of the second resistivity changing material.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: October 12, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Patent number: 7800093
    Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: September 21, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7802133
    Abstract: A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: September 21, 2010
    Assignee: Qimonda North America Corp.
    Inventors: KoonHee Lee, Ryan Patterson, Hoon Ryu, Klaus Nierle
  • Patent number: 7797511
    Abstract: A memory device includes a memory array containing a plurality of memory addresses. An input terminal receives a requested one of the memory addresses and a memory controller is configured to refresh a first refresh address in response to a comparison of the received memory address and the first refresh address. In certain embodiments, the first refresh address is refreshed if it does not conflict with the received memory. If the first refresh address and the received memory address conflict, a second refresh address is refreshed. The received memory address is accessed simultaneously with the refresh in exemplary embodiments.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: September 14, 2010
    Assignee: Qimonda North America Corp.
    Inventor: Thomas Vogelsang
  • Patent number: 7796424
    Abstract: A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: September 14, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7782703
    Abstract: Methods and apparatus that provide an additional level(s) of hierarchy within a bank of a Dynamic Random Access Memory (DRAM) are provided. The bank has a plurality of separately addressable sub-banks.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: August 24, 2010
    Assignee: Qimonda North America Corp.
    Inventor: Jong-Hoon Oh
  • Patent number: 7773438
    Abstract: An integrated circuit including an array of memory cells, volatile storage, non-volatile storage and a circuit. The circuit is configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sense first addresses. The circuit detects second defective memory cells via the sense first addresses and stores second addresses of the second defective memory cells in the volatile storage and in the non-volatile storage.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 10, 2010
    Assignee: Qimonda North America Corp.
    Inventor: Khaled Fekih-Romdhane
  • Patent number: 7765418
    Abstract: A supply voltage is provided in an integrated circuit by retrieving an indicator from a storage device and generating a supply voltage for use by the integrated circuit, the supply voltage being regulated responsive to the indicator being in a first state and unregulated responsive to the indicator being in a second state. Alternatively or additionally, an external voltage provided to the integrated circuit is compared with a threshold. The supply voltage is regulated responsive to the external voltage exceeding the threshold level and unregulated responsive to the external voltage falling below the threshold level.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: July 27, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Stephen Mann, Robert Ross, Iman Taha