Patents Assigned to Qualitau, Inc.
  • Patent number: 11175309
    Abstract: A wafer probe station system for reliability testing of a semiconductor wafer. The wafer probe station is capable of interfacing with interchangeable modules for testing of semiconductor wafers. The wafer probe station can be used with different interchangeable modules for wafer testing. Modules, such as probe card positioners and air-cooled rail systems, for example, can be mounted or docked to the probe station. The wafer probe station is also provided with a front loading mechanism having a rotatable arm that rotates at least partially out of the probe station chamber for wafer loading.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 16, 2021
    Assignee: QualiTau, Inc.
    Inventors: Edward McCloud, Jacob Herschmann
  • Patent number: 11054444
    Abstract: A voltage limiting circuit for limiting the voltage developed across a current sensing circuit and a method are disclosed. The voltage limiting circuit includes an input terminal configured to receive an input signal from the current sensing circuit, and an output terminal configured to receive an output signal from the current sensing circuit. A voltage sense circuit is connected to the input terminal and output terminal to detect that a predefined threshold voltage is developed between the input terminal and output terminal. An activation circuit receives a signal from the voltage sense circuit to activate the voltage limiting circuit, and a level shifting circuit interfaces the voltage sense circuitry to the activation circuitry and other circuits by level shifting signals to required levels.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 6, 2021
    Assignee: QualiTau, Inc.
    Inventor: James Borthwick
  • Patent number: 10890602
    Abstract: A universal multi-pin, adjustable probing assembly or manipulator for use in parametric and reliability testing of devices on a semiconductor wafer. The probing assembly can be mounted and adjusted on a metal platen using a magnetic field. The strength of the magnetic field can be adjusted by a switchable magnetic slab to which a block is connected via an arm. A probe head can be attached to a side face of the block, which includes a tilt control mechanism for tilting the probe head to ensure that probe tips land simultaneously on pads of dies. The probe head also includes four adjusting mechanisms for translation in the X, Y, and Z directions, as well as rotation about the Z axis.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 12, 2021
    Assignee: QualiTau, Inc.
    Inventors: Mirtcha Lupashku, Remy Orans
  • Patent number: 10690715
    Abstract: A signal distribution apparatus for distributing a stress signal to a plurality of devices under test (DUTs) is disclosed. The distribution apparatus includes a single input that receives the stress voltage signal to be distributed, a plurality of outputs that distribute the stress voltage signal to the plurality of DUTs, and a plurality of integrated current limiter and switch circuits. Each integrated current limiter and switch circuit connects a DUT of the plurality of DUTs to the single input through one of the plurality of outputs, and includes at least one combined switching and current limiting element.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: June 23, 2020
    Assignee: QualiTau, Inc.
    Inventor: James Borthwick
  • Patent number: 9772351
    Abstract: Pulsed current circuitry for electromigration testing of semiconductor integrated circuits and components. The circuit includes a multiplexer that outputs analog voltage pulses, and is capable of generating both bipolar and unipolar voltage pulses. At least one operational amplifier and resistor receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses. A charge booster circuit is provided for minimizing overshoots and undershoots during transitions between current levels in the test circuit.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: September 26, 2017
    Assignee: QualiTau, Inc.
    Inventors: Jens Ullmann, Gedaliahoo Krieger, James Borthwick
  • Patent number: 9196516
    Abstract: A wafer temperature measurement tool for measuring the surface temperature of a semiconductor wafer. The tool can be used to measure temperature on different parts of the wafer to provide a high resolution temperature distribution map. The tool includes an internal calibrated weight that is slidably disposed within a tool body. A temperature sensor is attached to the bottom of the weight. Ceramic stands are attached to the bottom of the tool body. Gravity pulls down on the weight such that the temperature sensor contacts the wafer when the ceramic stands of the tool body are placed on the wafer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 24, 2015
    Assignee: Qualitau, Inc.
    Inventors: Edward McCloud, David VandenBerg
  • Publication number: 20140269822
    Abstract: A wafer temperature measurement tool for measuring the surface temperature of a semiconductor wafer. The tool can be used to measure temperature on different parts of the wafer to provide a high resolution temperature distribution map. The tool includes an internal calibrated weight that is slidably disposed within a tool body. A temperature sensor is attached to the bottom of the weight. Ceramic stands are attached to the bottom of the tool body. Gravity pulls down on the weight such that the temperature sensor contacts the wafer when the ceramic stands of the tool body are placed on the wafer.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: QUALITAU, INC.
    Inventors: Edward McCloud, David VandenBerg
  • Patent number: 7888951
    Abstract: In accordance with an aspect, a thermally-controllable integrated unit is configured to hold devices under test. The integrated unit includes at least one heater board, comprised of a thermally-conductive material and provided with at least one global heater configured to globally heat the DUT board. A DUT board of the integrated unit includes a DUT board in thermal contact with the at least one heater board, the DUT board including a plurality of sockets, each socket configured to hold at least one DUT. The DUT has conductor paths to conduct electrical signals between test equipment and the terminals of DUTs in the sockets. Each socket includes an associated temperature sensor and a separately controllable local heater configured to, based on a temperature indication from the temperature sensor, heat a DUT in that socket.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: February 15, 2011
    Assignee: QualiTau, Inc.
    Inventors: Mirtcha Lupashku, Jacob Herschmann, Gedaliahoo Krieger
  • Patent number: 7812589
    Abstract: A current source is provided with two resistor banks, and digital potentiometers are used to control how much each resistor bank affects the resulting output current. Furthermore, when the digital potentiometers are at a particular setting such that a particular resistor bank does not affect the resulting output current (i.e., the resistor bank is “inactive”), the resistance of that resistor bank can be switched without affecting the output current, thus minimizing or eliminating discontinuities in the output current during a current sweep operation. Thus, for example, when a resistor bank meets its threshold and becomes inactive, the resistance of the inactive resistor bank may be switched, and then the digital potentiometer setting may be changed to facilitate smoothly reactivating that resistor bank, with the new resistance.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: October 12, 2010
    Assignee: QualiTau, Inc.
    Inventors: James Borthwick, Peter P. Cuevas, Tal Raichman
  • Publication number: 20100201389
    Abstract: In accordance with an aspect, a thermally-controllable integrated unit is configured to hold devices under test. The integrated unit includes at least one heater board, comprised of a thermally-conductive material and provided with at least one global heater configured to globally heat the DUT board. A DUT board of the integrated unit includes a DUT board in thermal contact with the at least one heater board, the DUT board including a plurality of sockets, each socket configured to hold at least one DUT. The DUT has conductor paths to conduct electrical signals between test equipment and the terminals of DUTs in the sockets. Each socket includes an associated temperature sensor and a separately controllable local heater configured to, based on a temperature indication from the temperature sensor, heat a DUT in that socket.
    Type: Application
    Filed: February 10, 2009
    Publication date: August 12, 2010
    Applicant: QUALITAU, INC.
    Inventors: Mirtcha LUPASHKU, Jacob HERSCHMANN, Gedaliahoo KRIEGER
  • Publication number: 20100052633
    Abstract: A current source is provided with two resistor banks, and digital potentiometers are used to control how much each resistor bank affects the resulting output current. Furthermore, when the digital potentiometers are at a particular setting such that a particular resistor bank does not affect the resulting output current (i.e., the resistor bank is “inactive”), the resistance of that resistor bank can be switched without affecting the output current, thus minimizing or eliminating discontinuities in the output current during a current sweep operation. Thus, for example, when a resistor bank meets its threshold and becomes inactive, the resistance of the inactive resistor bank may be switched, and then the digital potentiometer setting may be changed to facilitate smoothly reactivating that resistor bank, with the new resistance.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 4, 2010
    Applicant: QUALITAU, INC.
    Inventors: James BORTHWICK, Peter P. CUEVAS, Tal RAICHMAN
  • Patent number: 7602205
    Abstract: An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: October 13, 2009
    Assignee: Qualitau, Inc.
    Inventor: Jens Ullmann
  • Patent number: 7602201
    Abstract: A test socket assembly is for use in testing integrated circuits. A single piece socket is formed substantially of an insulating material and having a plurality of holes formed therein configured to receive a plurality of electrically conductive springs. Each hole of the single piece socket has therein a separate one of the electrically conductive springs. A test socket includes a plurality of pins configured to receive leads of an integrated circuit, the pins of the test socket extending into the plurality of holes of the single piece socket with each pin engaging a spring, wherein the single piece socket is positioned on a circuit board with the plurality of holes being in alignment with electrical contacts on the circuit board such that the plurality of springs are electrically interconnecting the contacts and the plurality of pins. The single -piece socket is comprised substantially of a high-temperature insulating material, such as ceramic.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: October 13, 2009
    Assignee: Qualitau, Inc.
    Inventors: Jose Ysaguirre, Jens Ullmann, Adalberto M. Ramirez, Robert J. Sylvia
  • Patent number: 7598760
    Abstract: A strip-shaped package is provided that can accept a single die up to many dice. Conduction paths are printed (or otherwise integrally formed) thereon to the edge of the package, and a complementary socket may be provided that, in combination with the strip-shaped package, provides for electrical connection to test electronics without the use of package leads. The strip-shaped package may be made of ceramic or other temperature resistant material. The strip-shaped package may have at least one “well” location in which the die or dice may be affixed to the strip-shaped package. The strip may have notches configured to function as separators between the individual die housings (and related integrally-formed conduction paths).
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: October 6, 2009
    Assignee: Qualitau, Inc.
    Inventors: Thomas G. Bensing, Adalberto M. Ramirez, Jens Ullmann, Jacob Herschmann, Robert J. Sylvia, Maurice C. Evans
  • Publication number: 20090206869
    Abstract: An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 20, 2009
    Applicant: QUALITAU, INC.
    Inventor: Jens Ullmann
  • Patent number: 7576550
    Abstract: A parametric test system is for testing devices in dice in a semiconductor wafer, each die having a plurality of pads for electrically connecting to the device in the die. A tester of the system has a plurality of input/output lines for providing and receiving electrical signals during a device test. Multiplexer circuitry of the test system includes a plurality of networks of automated switches. The multiplexer circuitry is configured to receive electrical signals on the input lines from the tester and to provide the electrical signals to a wafer prober, wherein the multiplexer circuitry is configured to restrict how the electrical signals can be provided to the networks of automated switches. As a result of the multiplexer being configured to restrict how the electrical signals can be provided to the networks of automated switches, the configuration of the networks of automated switches can be simplified.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: August 18, 2009
    Assignee: Qualitau, Inc.
    Inventors: Shahriar Mostarshed, Michael L. Anderson
  • Patent number: 7511517
    Abstract: A semi-automatic multiplexing system for automated semiconductor wafer testing employs a jumper block for each device type in the semiconductor wafer to be tested, each jumper block having inputs for receiving a test input/output line, a plurality of block contacts corresponding to pads of a device to be tested, and manually set connectors or jumper cables for selectively interconnecting jumper block inputs to block contacts. A multiplexer is then used for selectively connecting tester input/output lines to the jumper blocks, thereby reducing the number of relays required for connecting test signals to the devices in the semiconductor wafer.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: March 31, 2009
    Assignee: QualiTau, Inc.
    Inventors: Shahriar Mostarshed, Michael L. Anderson
  • Publication number: 20080315900
    Abstract: A test socket assembly is for use in testing integrated circuits. A single piece socket is formed substantially of an insulating material and having a plurality of holes formed therein configured to receive a plurality of electrically conductive springs. Each hole of the single piece socket has therein a separate one of the electrically conductive springs. A test socket includes a plurality of pins configured to receive leads of an integrated circuit, the pins of the test socket extending into the plurality of holes of the single piece socket with each pin engaging a spring, wherein the single piece socket is positioned on a circuit board with the plurality of holes being in alignment with electrical contacts on the circuit board such that the plurality of springs are electrically interconnecting the contacts and the plurality of pins. The single -piece socket is comprised substantially of a high-temperature insulating material, such as ceramic.
    Type: Application
    Filed: June 22, 2007
    Publication date: December 25, 2008
    Applicant: QUALITAU, INC.
    Inventors: Jose Ysaguirre, Jens Ullmann, Adalberto M. Ramirez, Robert J. Sylvia
  • Publication number: 20080315862
    Abstract: An instrument is configured to coordinate execution of a plurality of experiments employing a plurality of source measurement units (SMU's) to characterize a plurality of devices under test (DUT's). Each experiment controller, of a plurality of experiment controllers, is configured to manage one of the plurality of experiments by, at least in part, controlling the SMU's allocated to that experiment. A main controller is configured to interoperate with a host to manage the experiment controllers. For example, the instrument may be configured to provide experiment parameters to the SMU's prior to execution of the experiments. In one aspect, the main controller is configured to receive experiment parameters from a host controller external to the instrument. At least in part based on the received experiment parameters, the main controller configure which experiment controllers are to manage which experiment.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Applicant: QUALITAU, INC.
    Inventor: Shay-Tsion Daniel
  • Publication number: 20080238451
    Abstract: A parametric test system is for testing devices in dice in a semiconductor wafer, each die having a plurality of pads for electrically connecting to the device in the die. A tester of the system has a plurality of input/output lines for providing and receiving electrical signals during a device test. Multiplexer circuitry of the test system includes a plurality of networks of automated switches. The multiplexer circuitry is configured to receive electrical signals on the input lines from the tester and to provide the electrical signals to a wafer prober, wherein the multiplexer circuitry is configured to restrict how the electrical signals can be provided to the networks of automated switches. As a result of the multiplexer being configured to restrict how the electrical signals can be provided to the networks of automated switches, the configuration of the networks of automated switches can be simplified.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: QUALITAU, INC.
    Inventors: Shahriar Mostarshed, Michael L. Anderson