Patents Assigned to Qualitau, Inc.
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Patent number: 7429856Abstract: A particular configuration of voltage source measurement (VSM) circuitry minimizes common mode errors in measurement of current through a device under test (DUT), even across a wide range of output voltages. The current IDUT is not affected by common-mode errors, since the current measurement is based on the output voltage of an operational amplifier or a differential amplifier, and the circuit configuration is such that the current measurement is made while the operation amplifier or differential amplifier has very low common-mode input voltage.Type: GrantFiled: November 20, 2007Date of Patent: September 30, 2008Assignee: Qualitau, Inc.Inventor: Jens Ullmann
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Patent number: 7405573Abstract: An interconnect assembly is for use in connection with a semiconductor device under test (DUT) having a plurality of leads to electronic test equipment. The interconnect assembly includes a cable including a plurality of wires with at least one wire for sensing a signal from a DUT, at least one wire for a forcing signal to the DUTY and at least one wire for a guarding signal driven by the same electrical potential as the forcing signal. A male connector includes the plurality of wires, an outer metal coating surrounding the plurality of wires, and an insulating coating around the outer metal coating. A receptacle connector is for receiving the male connector and plurality of wires with corresponding contacts.Type: GrantFiled: March 16, 2005Date of Patent: July 29, 2008Assignee: QualiTau, Inc.Inventor: Peter P. Cuevas
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Patent number: 7172450Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated circuit package and having a plurality of holes for receiving leads extending from the package. A second member has a plurality of wire contacts for engaging the leads, the first and second members being arranged to permit relative lateral translation thereof. A support frame includes a first portion which physically engages the first member and a second portion which physically engages the second member. A lever or handle is attached to the second portion and includes a cam surface for engaging a cam follower on the first portion for imparting relative lateral motion between the two members whereby the package leads physically engage wires of the second member.Type: GrantFiled: January 11, 2006Date of Patent: February 6, 2007Assignee: Qualitau, Inc.Inventors: Robert James Sylvia, Adalberto M. Ramirez, Jens Ullmann, Jose Ysaguirre, Peter P. Cuevas, Maurice C. Evans
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Patent number: 7151389Abstract: A dual channel source measurement unit for reliability testing of electrical devices provides a voltage stress stimulus to a device under test and monitors degradation to the device under test caused by the stress simulator. The dual channel source measurement unit decouples the stress and monitor portions of the unit so that the requirements of each can be optimized. Deglitching and current clamp switches can be incorporated in the dual channel source measurement unit to prevent glitches in the switching circuitry and to limit or clamp current flow to or from the monitor and stress sources.Type: GrantFiled: March 2, 2005Date of Patent: December 19, 2006Assignee: Qualitau, Inc.Inventors: Tal Raichman, Peter P. Cuevas, James Borthwick, Michael A. Casolo
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Patent number: 7126361Abstract: A probe card is vertically mounted generally perpendicular to a wafer undergoing life tests in a heated environment to limit exposure of the probe card to heat from the wafer chuck. The probe card and probe head assembly are mounted on a support rail which has one or more channels for the flow of cool air to a probe head assembly and the probe card, while it shields the flex cable from the hot chuck. The cool air flow disrupts convective hot air flow upwards from the heated chuck to the probe card and probe head and facilitates cooling of the probe card and probe head.Type: GrantFiled: August 3, 2005Date of Patent: October 24, 2006Assignee: Qualitau, Inc.Inventors: Michael L. Anderson, Edward A. McCloud, Shahriar Mostarshed, Michael A. Casolo
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Patent number: 7098648Abstract: In an electrical circuit for testing electrical current using a plurality of precision resistors connected in parallel or in series, a range finder for receiving the current to be measured with the voltage drop across the range finder being indicative of a current sub-range for measurement. In a preferred embodiment, a range finder has a first bipolar transistor and a second bipolar transistor connected in parallel and in opposite polarity with the emitter and base of each transistor connected together whereby each transistor functions as an emitter-base diode.Type: GrantFiled: June 14, 2004Date of Patent: August 29, 2006Assignee: Qualitau, Inc.Inventors: Gedaliahoo Krieger, Peter P. Cuevas, James Borthwick
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Patent number: 7082676Abstract: An anti-electrostatic discharge (ESD) tool for engaging electronic device under test (DUT) boards whereby ESD damage to the tested devices is prevented. The tool includes an aluminum support frame, guides on opposing edges of one side of the frame for slidably receiving a DUT board, and at least one electrical shorting connector extending from the frame and electrically connecting and shorting socket connectors and leads of electronic devices when the DUT board is inserted into the guides. The electrical shorting connector preferably comprises an array of fine wire brushes which have sufficient rigidity and flexibility for engaging solder points on the DUT board for the socket connectors.Type: GrantFiled: August 5, 2003Date of Patent: August 1, 2006Assignee: Qualitau, Inc.Inventors: Adalberto M. Ramirez, Robert J. Sylvia
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Patent number: 7049713Abstract: A pulsed current generator circuit for providing current pulses to a device under test includes a current source for applying a current to the device under test and a controlled current shunt for shunting current from the device under test. A booster circuit is provided for supplying a booster current to the device under test when the controlled current shunt is opened and current again flows through the device under test, thereby facilitating recharge of a parasitic capacitance associated with the device under test.Type: GrantFiled: December 10, 2003Date of Patent: May 23, 2006Assignee: Qualitau, Inc.Inventors: Peter Cuevas, Gedaliahoo Krieger, Maurice Evans, Jens Ullmann
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Publication number: 20050206367Abstract: In an electrical for testing electrical current using a plurality of precision resistors connected in parallel or in series, a range finder for receiving the current to be measured with the voltage drop across the range finder being indicative of a current sub-range for measurement. In a preferred embodiment, a range finder comprises a first bipolar transistor and a second bipolar transistor connected in parallel and in opposite polarity with the emitter and base of each transistor connected together whereby each transistor functions as an emitter-base diode.Type: ApplicationFiled: June 14, 2004Publication date: September 22, 2005Applicant: QualiTau, Inc.Inventors: Gedaliahoo Krieger, Peter Cuevas, James Borthwick
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Publication number: 20050194963Abstract: A dual channel source measurement unit for reliability testing of electrical devices provides a voltage stress stimulus to a device under test and monitors degradation to the device under test caused by the stress simulator. The dual channel source measurement unit decouples the stress and monitor portions of the unit so that the requirements of each can be optimized. Deglitching and current clamp switches can be incorporated in the dual channel source measurement unit to prevent glitches in the switching circuitry and to limit or clamp current flow to or from the monitor and stress sources.Type: ApplicationFiled: March 2, 2005Publication date: September 8, 2005Applicant: QualiTau, Inc.Inventors: Tal Raichman, Peter Cuevas, James Borthwick, Michael Casolo
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Patent number: 6798228Abstract: A test socket assembly for use in testing integrated circuits includes a spring holder plate having a plurality of holes for receiving a plurality of electrically conducting springs, and a plurality of electrically conducting springs in the plurality of holes. A test socket including a plurality of pins for receiving leads of an integrated circuit is mounted on the spring holder plate with the pins extending into the plurality of holes in the spring holder plate with each pin engaging a spring. The holder plate is positionable on a printed circuit board with the plurality of holes in the spring holder plate being in alignment with electrical contacts or pads on the printed circuit board, the plurality of springs electrically interconnecting the contacts and the plurality of pins.Type: GrantFiled: January 10, 2003Date of Patent: September 28, 2004Assignee: QualiTau, Inc.Inventor: Peter Cuevas
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Patent number: 6784000Abstract: Electromigration testing is accelerated in the batch fabrication of semiconductor integrated circuits by forming test structures during the metal deposition phase of the batch fabrication process. Test metal lines can be formed on steps etched in a silicon oxide insulating layer with the vertical walls of the steps being greater than twice the thickness of the deposited metal whereby metal is not deposited on the side walls. Alternatively, test lines in the deposit metal layer can be formed by laser ablation or by ultrasound erosion. In another embodiment, electromigration tests are performed directly on the deposit metal layer through use of spaced elongated electrical contacts placed on the deposited metal layer surface. The elongated contacts can be wires of known diameter and length, or the elongated contacts can comprise a plurality of point contacts.Type: GrantFiled: July 31, 2001Date of Patent: August 31, 2004Assignee: QualiTau, Inc.Inventors: Robert Sikora, Gedaliahoo Kreiger, Yongbum Cuevas
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Publication number: 20040135592Abstract: A test socket assembly for use in testing integrated circuits includes a spring holder plate having a plurality of holes for receiving a plurality of electrically conducting springs, and a plurality of electrically conducting springs in the plurality of holes. A test socket including a plurality of pins for receiving leads of an integrated circuit is mounted on the spring holder plate with the pins extending into the plurality of holes in the spring holder plate with each pin engaging a spring. The holder plate is positionable on a printed circuit board with the plurality of holes in the spring holder plate being in alignment with electrical contacts or pads on the printed circuit board, the plurality of springs electrically interconnecting the contacts and the plurality of pins.Type: ApplicationFiled: January 10, 2003Publication date: July 15, 2004Applicant: QualiTau, Inc.Inventor: Peter Cuevas
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Patent number: 6592389Abstract: A minimal insertion force socket for use in testing DIP integrated circuits having a plurality of leads extending therefrom, the socket plate having a plurality of holes arranged in two parallel rows for receiving the leads from the integrated circuit, and a plurality of wires anchored on the socket plate and arranged in two parallel partially interdigitated sets with each wire cooperating with a hole for engaging a lead of the integrated circuit. The working distance from a lead contact point on each wire to an anchor point on the interdigitated portion of each wire is increased relative to the working distance of aligned wires in the two parallel sets.Type: GrantFiled: May 29, 2002Date of Patent: July 15, 2003Assignee: QualiTau, Inc.Inventor: Peter Cuevas
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Patent number: 6565373Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated package and having a plurality of first holes for receiving leads extending from the package. A second member has a plurality of wires for engaging the leads, each wire being anchored at ends to the second member with an intermediate portion engaging a lead. Each intermediate portion is aligned with a first hole and capable of being flexed out of alignment with the first hole for insertion of an integrated circuit package into the socket. The first member includes a second plurality of holes aligned with the wires of the second member, and an actuator has a plurality of pins arranged to extend into the second plurality of holes for engaging the plurality of wires and flexing the intermediate portions of the wires out of alignment with the first plurality of holes.Type: GrantFiled: May 29, 2002Date of Patent: May 20, 2003Assignee: QualiTau, Inc.Inventor: Peter Cuevas
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Publication number: 20030003790Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated package and having a plurality of first holes for receiving leads extending from the package. A second member has a plurality of wires for engaging the leads, each wire being anchored at ends to the second member with an intermediate portion engaging a lead. Each intermediate portion is aligned with a first hole and capable of being flexed out of alignment with the first hole for insertion of an integrated circuit package into the socket. The first member includes a second plurality of holes aligned with the wires of the second member, and an actuator has a plurality of pins arranged to extend into the second plurality of holes for engaging the plurality of wires and flexing the intermediate portions of the wires out of alignment with the first plurality of holes.Type: ApplicationFiled: May 29, 2002Publication date: January 2, 2003Applicant: QualiTau, Inc.Inventor: Peter Cuevas
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Publication number: 20030003791Abstract: A minimal insertion force socket for use in testing DIP integrated circuits having a plurality of leads extending therefrom, the socket plate having a plurality of holes arranged in two parallel rows for receiving the leads from the integrated circuit, and a plurality of wires anchored on the socket plate and arranged in two parallel partially interdigitated sets with each wire cooperating with a hole for engaging a lead of the integrated circuit. The working distance from a lead contact point on each wire to an anchor point on the interdigitated portion of each wire is increased relative to the working distance of aligned wires in the two parallel sets.Type: ApplicationFiled: May 29, 2002Publication date: January 2, 2003Applicant: QualiTau, Inc.Inventor: Peter Cuevas
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Patent number: 6469494Abstract: A programmable connector for use with a burn-in tester for manufactured integrated circuits is provided with an array of programming regions which can be selectively activated and deactivated to accommodate a specific testing configuration depending on the type of IC being tested and on the type of test being performed. The activation process is achieved using a conductive solution, applied selectively to the programming regions from a hand-held pen-type implement. The solution dries following application and serves to close a circuit between two electrically isolated conductive portions of the programming region. The solution is removable, using a solvent or other material, deactivation of the programming region for re-configuring the programmable connector.Type: GrantFiled: November 3, 1999Date of Patent: October 22, 2002Assignee: QualiTau, Inc.Inventor: Peter P. Cuevas
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Patent number: 6249137Abstract: A test circuit for applying bipolar current pulse to first and second terminals of device under test (DUT) includes a first DC current source and a first switch having a first common terminal, a second DC current source and a second switch having a second common terminal, and means for connecting a device under test between the first and second common terminals. A timing generator selectively controls conduction of the first switch and the second switch whereby when the first switch is closed the current from the second DC current source flows through the device under test and the first switch to a circuit ground, and when the second switch is closed the current from the first DC current course flows through the device under test and the second switch to a circuit ground. Pulse repetition rate and duty cycle of the current pulses are controlled by the control voltage pulses from the timing generator.Type: GrantFiled: October 14, 1999Date of Patent: June 19, 2001Assignee: Qualitau, Inc.Inventors: Gedaliahoo Krieger, Yongbum Cuevas
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Patent number: 6179640Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated circuit package and having a plurality of holes for receiving leads extending from the package. A second member has a plurality of wire contacts for engaging the leads, the first and second members being arranged to permit relative lateral translation thereof. A cam is provided for sliding the first member relative to the second member and moving leads extending through the holes in the first member into engagement with the contacts of the second member. A socket for dual in-line integrated circuit package (DIP) has two rows of holes in the first member, and two slots are provided in the second member each aligned with a row of holes. The wire contacts extend across each slot. For high temperature operation (greater than 250° C.) the first and second members comprise anodized aluminum or a ceramic, and the wires comprise Monel or other high temperature material.Type: GrantFiled: April 1, 1999Date of Patent: January 30, 2001Assignee: Qualitau, Inc.Inventors: Robert Sikora, Adalberto M. Ramirez, Maurice Evans, Yongbum (Peter) Cuevas, Robert Sylvia