Patents Assigned to QuickLogic Corporation
  • Patent number: 10775206
    Abstract: A sensor hub includes a bit packer that receives sensor data from a plurality of sensors and bit packs the sensor data so that the sensor ID, time stamp and each axis of the measured data is stored contiguously. The bit packer may compress the sensor data by removing the sensor ID and/or the time stamp in the sensor data. The bit packed sensor data is stored in batching memory. A bit unpacker receives the sensor data from the batching memory and unpacks the sensor data, e.g., so that the sensor ID, time stamp and each axis of the measured data is stored in its own word. Additionally, the bit unpacker may decompress the bit packed sensor data by reinserting the sensor ID and/or time stamp in the sensor data.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 15, 2020
    Assignee: QuickLogic Corporation
    Inventors: Rajasekaran Ramasubramanian, Dung Le
  • Patent number: 10456053
    Abstract: A wrist worn heart rate monitor includes a photoplethysmogram (PPG) sensor and an inertial sensor. Signals from the inertial sensor are used to identify and remove noise from the PPG signals. An initial heart rate value is selected from a number of heart rate candidates that remain in the resulting PPG spectrum and is used to track the heart rate of the user. The PPG spectrum is monitored while tracking the heart rate to determine if the selected initial heart rate value is in error. The PPG spectrum may be monitored by determining a correlation of possible heart rate candidates in each PPG spectrum to the previous heart rate candidates and resetting the heart rate value accordingly. Additionally or alternatively, the PPG spectrum may be monitored by determining when only a single heart rate candidate is present in consecutive PPG spectra and resetting the heart rate value accordingly.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 29, 2019
    Assignee: QuickLogic Corporation
    Inventor: Amir Abbas Emadzadeh
  • Patent number: 10197416
    Abstract: A wrist worn pedometer includes a multiple axis inertial sensor. Signals from each axis of the multiple axis inertial sensor are received and are separately analyzed to determine which axis is producing a stable periodic signal, which is selected as the counting axis, i.e., the axis to be used for counting steps. Additionally, the pedometer determines whether the counting axis is registering arm movement or footsteps. The user's steps are counted based on the detected events, e.g., detected peaks or intervals between peaks, on the signal from the counting axis. One step per detected event is counted if the counting axis is registering footsteps and two steps per detected event are counted if the counting axis is registering arm movement. If the stability of the selected counting axis is lost, another axis is selected as the counting axis if it is producing a stable periodic signal.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: February 5, 2019
    Assignee: QuickLogic Corporation
    Inventors: Duanduan Yang, Dong An, Ying Wu
  • Patent number: 10148270
    Abstract: A programmable logic device uses power island based design partitioning. Each power islands includes a plurality of programmable logic cells and a programmable routing network configurable to interconnect the plurality of programmable logic cells and configurable to interconnect with at least one other power island. When a power island is in an OFF state, the programmable logic cells within the power island are powered OFF. Feed-through routing connectors in the power island, however, may be statically or dynamically powered ON independently of the powered OFF state of the power island.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: December 4, 2018
    Assignee: QuickLogic Corporation
    Inventors: Pinaki Chakrabarti, Wilma W. Shiao, Ket-Chong Yap, Vishnu A. Patil, Lalit Narain Sharma
  • Patent number: 9811335
    Abstract: End-user software is used to select lists of values of control signals from a predetermined design of a processor, and a unique value of an opcode is assigned to each selected list of values of control signals. The assignments, of opcode values to lists of values of control signals, are used to create a new processor design customized for the end-user software, followed by synthesis, place and route, and netlist generation based on the new processor design, followed by configuring an FPGA based on the netlist, followed by execution of the end-user software in customized processor implemented by the FPGA. Different end-user software may be used as input to generate different assignments, of opcode values to lists of control signal values, followed by generation of different netlists. The different netlists may be used at different times, to reconfigure the same FPGA, to execute different end-user software optimally at different times.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: November 7, 2017
    Assignee: QuickLogic Corporation
    Inventors: Oleg Nikitovich Khainovski, Dan Aizenstros, Randy Ichiro Oyadomari, Timothy Saxe
  • Patent number: 9628083
    Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway networks. Some of the switches include multiple stages. The street network switch receives the signals from the feedback network switch, signals from neighboring highway network switches, and direct feedback from selected logic island outputs and provides outputs to the logic island. The street network switch includes multiple stages, where outputs to the logic island are provided directly by each stage in the street network switch. The output terminals of a first stage of the street network switch that are connected to the logic island are also connected to the second stage of the street network switch. The second stage of the street network switch receives feedback output signals from the feedback network and directly from the associated logic island.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: April 18, 2017
    Assignee: QuickLogic Corporation
    Inventors: Pinaki Chakrabarti, Vishnu A. Patil, Wilma W. Shiao
  • Patent number: 9287868
    Abstract: A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: March 15, 2016
    Assignee: QuickLogic Corporation
    Inventors: Vishnu A. Patil, Wilma W. Shiao, Tarachand Pagarani, Pinaki Chakrabarti
  • Patent number: 9118325
    Abstract: A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway and clock networks. Some of the switches include multiple stages. The feedback network switch receives signals from the logic island as well as from neighboring logic blocks and provides an output to one or more stages of the street network switch. The street network switch receives the signals from the feedback network switch and signals from neighboring highway network switches and provides an output to the logic island. A clock network switch may receive dedicated clock signals or high fan out signals as inputs and provides outputs to the street network switch. The highway network switch receives signals from the logic island and from neighboring highway network switches and provides an output to neighboring highway network switches.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: August 25, 2015
    Assignee: QuickLogic Corporation
    Inventors: Vishnu A. Patil, Karyampoodi Bhanu Prasanth, Wilma W. Shiao, Tarachand Pagarani, Pinaki Chakrabarti
  • Patent number: 8487652
    Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 16, 2013
    Assignee: QuickLogic Corporation
    Inventors: Ket-Chong Yap, Senani Gunaratna, Wilma Waiman Shiao
  • Patent number: 8261002
    Abstract: Embodiments of the present invention provide a unique capability of implementing a pair of pseudo-PHY interfaces using a bridge. From the host and device perspectives, the host and device communicate through a PHY interface. The bridge, however, avoids actually using a USB PHY interface. This PHY-less bridge allows communication between a host and a device at high speeds without high-power transceivers associated with a USB PHY interface. In accordance with the present invention, a host and a device may be coupled together using a PHY-less bridge using the same interface or translating between different interfaces by using a wrapper. Such PHY-less bridges include a UTMI-to-UTMI bridge, a UTMI-to-ULPI bridge, a ULPI-to-UTMI bridge and a ULPI-to-ULPI bridge, each avoiding the need for a USB PHY interface.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: September 4, 2012
    Assignee: QuickLogic Corporation
    Inventors: Eric So, Stephen U. Yao, Alan Shiu Lung Tsun
  • Patent number: 8091001
    Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: January 3, 2012
    Assignee: QuickLogic Corporation
    Inventors: Stephen U. Yao, Darwin D. Q. Samson, Ket-Chong Yap
  • Publication number: 20110298492
    Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
    Type: Application
    Filed: August 18, 2011
    Publication date: December 8, 2011
    Applicant: QuickLogic Corporation
    Inventors: Ket-Chong Yap, Senani Gunaratna, Wilma Waiman Shiao
  • Patent number: 8018248
    Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: September 13, 2011
    Assignee: QuickLogic Corporation
    Inventors: Ket-Chong Yap, Senani Gunaratna, Wilma Waiman Shiao
  • Patent number: 7646216
    Abstract: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: January 12, 2010
    Assignee: QuickLogic Corporation
    Inventors: Wilma Waiman Shiao, Stephen U. Yao, Ket-Chong Yap
  • Patent number: 7482834
    Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: January 27, 2009
    Assignee: QuickLogic Corporation
    Inventors: Ajithkumar V. Dasari, Wilma Waiman Shiao, Tarachand G. Pagarani
  • Patent number: 7443222
    Abstract: An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: October 28, 2008
    Assignee: QuickLogic Corporation
    Inventors: Timothy Saxe, Senani Gunaratna, Stephen U. Yao
  • Publication number: 20080133988
    Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic.
    Type: Application
    Filed: November 30, 2006
    Publication date: June 5, 2008
    Applicant: QUICKLOGIC CORPORATION
    Inventors: Stephen U. Yao, Darwin D.Q. Samson, Ket-Chong Yap
  • Publication number: 20080122483
    Abstract: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 29, 2008
    Applicant: QuickLogic Corporation
    Inventors: Wilma Waiman Shiao, Stephen U. Yao, Ket-Chong Yap
  • Publication number: 20080094103
    Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Applicant: QUICKLOGIC CORPORATION
    Inventors: Ajithkumar V. Dasari, Wilma Waiman Shiao, Tarachand G. Pagarani
  • Publication number: 20080074141
    Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 27, 2008
    Applicant: QuickLogic Corporation
    Inventors: Ket-Chong Yap, Senani Gunaratna, Wilma Waiman Shiao