Abstract: An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.

Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic.

Abstract: An apparatus and method of reducing power consumption across a switch, such as an unprogrammed antifuse, is provided. The invention applies to antifuses, other switches such as transistor based switches, (e.g., FLASH, EEPROM and/or SRAM) and other devices exhibiting a leakage current, especially during a sleep or stand-by mode. During a sleep mode, such switches or other devices may be uncoupled from signals driving the switches, then terminals of each switch may be coupled to a common potential or allowed to float to a common potential thereby eliminating or reducing leakage currents through the switches.

Abstract: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.

Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.

Abstract: An antifuse, which has a programmable material disposed between two conductive elements, is programmed using multiple current pulses of opposite polarity. The first pulse has a current that is insufficient to fully program the antifuse, i.e., produce a desired level of resistance. In one embodiment the first pulse is current limited. The first pulse advantageously drives a conductive filament from one conductive element through the antifuse material, which may be, e.g., amorphous silicon. The conductive filament from the first pulse, however, has a limited cross sectional area. A programming pulse having the same voltage with opposite polarity and a current with increased magnitude is used to drive material from the other conductive element into the antifuse material, which increases the cross sectional area of the conductive filament thereby reducing resistance. Additional programming pulses, as well as current limited pulses, may be used if desired.

Abstract: A differential charge pump includes a transient reducing circuit that provides multiple switching current paths to reduce transients caused by the charge transfer as the charge pump is switched. The differential charge pump includes separate current sources in the transient reducing circuit that are switchably coupled to the non-active current source in the charge pump. In one embodiment, each current sources include a static current source and a variable current source that is controlled by a common mode feedback circuit. The variable current source may produce a current with less magnitude than the current produced by the static current source.

Abstract: A differential charge pump includes a transient reducing circuit that provides multiple switching current paths to reduce transients caused by the charge transfer as the charge pump is switched. The differential charge pump includes separate current sources in the transient reducing circuit that are switchably coupled to the non-active current source in the charge pump. In one embodiment, each current sources include a static current source and a variable current source that is controlled by a common mode feedback circuit. The variable current source may produce a current with less magnitude than the current produced by the static current source.

Abstract: A voltage regulator with a variable compensation capacitor is capable of driving a large variable dynamic current load. The regulator includes an error amplifier and an output stage amplifier. The variable compensation capacitor is disposed between the output terminal of the error amplifier and the output terminal of the output stage amplifier. In one embodiment, a NMOS transistor is disposed between the output terminal of the output stage amplifier and the variable compensation capacitor. The variable compensation capacitor may be, e.g., a PMOS transistor with the source and drain tied together. In one embodiment, a plurality of regulators is included on chip, e.g., such as a programmable device, where the output terminals of each regulator is tied together and used to drive the same load.

Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors.

Abstract: In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.

Abstract: In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.

Abstract: A programmable device, such as a field programmable gate array, includes a main field that is programmable by the user and at least one embedded portion that is reserved to be programmed with a standard circuit design that is configured, for example, by the manufacturer. The embedded portion is similar to the main field, i.e., it has the same programmable structure, however, the embedded portion is not accessible to the user. In some embodiments, the embedded portion may be pre-programmed with the standard circuit design and in other embodiments the embedded portion is programmed while the user programs the main field. The programmable device may also include signature bits that are used by the programming unit to identify the programmable device as having the embedded portion and which standard circuit design to program into the embedded portion. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device.

Abstract: An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.

Abstract: An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.

Abstract: A plurality of configurable computational units are embedded in a programmable device, such as a field programmable gate array. Each configurable computational unit includes an adder circuit that is switchably coupled to a multiplier circuit and an accumulator circuit. The configurable computational unit may be configured permanently or on-the-fly to perform desired arithmetic type functions efficiently and effectively. For example, the computational unit may be configured for digital signal processing functions, filtering functions, and algorithm functions. The computational units may be cascaded by programmably connecting the computational units together, e.g., through the routing resources of the programmable device.

Abstract: A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor.

Abstract: A lower metal plate having a strip-like opening is used in a bond pad structure having metalplugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper metal plate, through the strip-like opening, and to a foundation layer upon which the lower metal plate is disposed. The bond pad structure can be fabricated using the same semiconductor processing steps used to fabricate amorphous silicon antifuse structures having metal plugs.

Abstract: The present invention provides a method and apparatus for high yield improvements in programmable logic devices using redundancy. The present invention concerns a programmable logic device comprising a plurality of routings lines coupled to a plurality of logic blocks when programmed. During programming, a path is routed through the routing lines by programming the selected programmable elements. The selected programmable elements are located at each interconnect point between at least two routing lines or two segments of a routing lines along the path. The programmable elements include at least two interconnect circuits coupled in parallel. The programmable element is successfully programmed when at least one of the interconnect circuits is functional after programming.

Abstract: A programmable device, such as a field programmable gate array, includes at least one signature bit that is used to indicate whether the programmable device has fewer than all the logic blocks accessible to the user. The signature bit may be programmed after the manufacture of the programmable device or may be hard wired during the manufacture of the device. The programming unit recognizes the configuration of the signature bit and restricts access to particular logic blocks based on the configuration. Thus, a large programmable unit may become a smaller “virtual” programmable device by altering the configuration of the signature bit, which is recognized by the programming unit. Consequently, the manufacturer may test market programmable devices of differing sizes to determine demand without incurring the costs associated with producing a completely new product line.