Abstract: Improved apparatus and methods for programming anti-fuse devices utilized in programmable semiconductor chips are described. An anti-fuse device circuit is disclosed wherein an anti-fuse device is connected between two programming transistors, and each programming transistor is connected to a separate voltage supply bus and to a control bus network having, for example, a common control bus or separate control buses. Interconnection structures of anti-fuse devices can be formed and a targeted anti-fuse device can be programmed by connecting a programming voltage to the first associated supply bus, by connecting another voltage or ground potential to the second associated supply bus, and by turning on the appropriate control bus line or lines so that the programming transistors conduct to provide a voltage differential across the targeted anti-fuse device.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation.

Abstract: A method for reducing the resistance of a programming path through a programmable antifuse from a programming voltage to ground. A previously programmed helper antifuse connected somewhere along a two branch programming path is connected to either the programming voltage or to ground. As a result, a three branch programming path is established from the programming voltage to the antifuse to be programmed and from the antifuse to be programmed to ground. By adding the third branch to the programming path, the resistance of the programming path is reduced, thereby allowing a higher voltage to be dropped across the antifuse to be programmed during programming and thereby allowing increased current flow through the antifuse to be programmed during programming. In another embodiment, two or more helper antifuses are used to establish a four or more branch programming path having a still lower resistance from the programming voltage to ground.

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation.

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs.

Abstract: A method for determining an electrical characteristic (such as a resistance) of an antifuse of a programmable device.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuse are formed over the intermetal dielectric. The antifuse are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.