Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.

Abstract: Provided in the present application are a data processing method and apparatus based on data coding, and a device. The method comprises: performing N-channel error correction coding on data to be processed that is in information to be processed, so as to obtain N pieces of coded data to be processed; by using coded meta-channel data obtained by means of error correction coding, performing redundancy processing on the coded data to be processed, so as to obtain N pieces of response data; and then performing error correction decoding on the N pieces of response data, so as to obtain processing result information of the information to be processed.

Abstract: The present invention disclosures a phase change memory unit, wherein comprising from bottom to top: a bottom electrode, a heating electrode, a phase change unit and a top electrode, the phase change unit is a longitudinally arranged column, which comprises: a cylindrical selector layer, a circular barrier layer and a circular phase change material layer form inside to outside; wherein, the bottom electrode, the heating electrode and the circular phase change material layer are sequentially connected, and the selector layer is connected to the top electrode. The present invention using trench sidewall deposition or via filling, forming the cylindrical phase change unit which is a circular nested structure, which can improve reliability of a device, greatly reduce volume of a phase change operation area and heat energy required, thus heating efficiency is improved obviously, the power consumption of the device is reduced, and high-density storage is realized.

Abstract: A structural encoding unit and an error correction decoding unit are divided. The structure encoding unit is divided into input branch processor and an input proxy processor; and the error correction decoding unit is divided into an output routing processor, an output proxy processor, an adjudication branch processor, an adjudication proxy processor and a voting processor. The input branch processor is used for duplicating and distributing messages, the arbitration branch processor is used for duplicating and distributing data, the voting processor is used for performing voting, and the output routing processor is used for selecting an output result from processing results of the output proxy processor according to a voting result of the voting processor.

Abstract: Provided are a data processing system and method based on dynamic redundancy heterogeneous encoding, and a device. The method comprises: respectively performing error correction encoding on information to be processed and a processing rule, so as to form encoded information to be processed and an encoded processing rule; processing, by using the encoded processing rule, the encoded information to be processed, so as to obtain response data; and then performing error correction decoding on N pieces of response data, so as to obtain processing result information of the information to be processed.

Abstract: The present invention relates to an improved process for the preparation of (3S,4R)-3-ethyl-4-(3H-imidazo[1,2-a]pyrrolo[2,3-e]pyrazin-8-yl)-N-(2,2,2-trifluoroethyl)pyrrolidine-1-carboxamide formula-1. The present invention relates to crystalline form of 8-((3R,4S)-4-ethylpyrrolidin-3-yl)-3H-imidazo[1,2-a]pyrrolo[2,3-e]pyrazine compound of formula-2. The present invention also relates dibenzoyl-L-tartaric acid salt and 4-nitrobenzoic acid salt of (3S,4R)-3-ethyl-4-(3H-imidazo[1,2-a]pyrrolo[2,3-e]pyrazin-8-yl)-N-(2,2,2-trifluoro ethyl)pyrrolidine-1-carboxamide and its polymorph forms which are useful in the preparation of pure Upadacitinib. The present invention also relates to a crystalline form of Upadacitinib tartrate and its process thereof.

Abstract: The present invention relates to an improved process for the preparation of 5-[(4-bromo-2-fluorophenyl)amino]-4-fluoro-N-(2-hydroxyethoxy)-1-methyl-1H-benzimidazole-6-carboxamide represented by the following structural formula-1, which is referred to as Binimetinib

Abstract: A razor head includes a frame including two opposing long side walls and two opposing short side walls, connectors each connecting two points of the frame in an interior of the frame, and elongated blades arranged on an inner side of the frame. The blades are coupled to only two of the connectors, the two connectors to which the blades are coupled connecting the two long side walls to each other. In a case where a position in the frame in a longitudinal direction is represented by a percentage, when a middle of the frame in the longitudinal direction is 0% and two ends of the frame in the longitudinal direction that correspond to inner surfaces of the two short side walls are 100%, the two connectors to which the blades are coupled are each arranged in a range from 30% to 90% between the middle and the two ends.

Abstract: The present invention relates to novel crystalline polymorphs of 1-[(3R)-3-[4-amino-3(4-phenoxy phenyl)-1H-pyrazolo[3,4-d]pyrimidin-1-yl]-1-piperidinyl]-2-propen-1-one represented by the following structural formula-1 and process for preparation thereof.

Abstract: The present invention relates to novel crystalline polymorphs of sodium (4R,12aS)-9-{[(2,4-difluorophenyl) methyl]carbamoyl}-4-methyl-6,8-dioxo-3,4,6,8,12,12a-hexahydro-2H-pyrido[1?,2?:4,5] pyrazino[2,1-b] [1,3] oxazin-7-olate represented by the following structural formula-1a and process for their preparation. The present invention further relates to novel solvated forms of sodium (4R,12aS)-9-{[(2,4-difluoro phenyl) methyl] carbamoyl}-4-methyl-6,8-dioxo-3,4,6,8,12,12a-hexahydro-2H-pyrido[1?,2?:4,5] pyrazino[2,1-b][1,3] oxazin-7-olate compound of formula-1a and process for their preparation.

Abstract: The present invention discloses a vessel power safety control system and operating method thereof. The vessel power safety control system includes a load power management module, a real-time monitoring module, an integration module and a power module. The present invention can assist the autonomous ship as any occurrence of fault during navigation. Once the accident occurs, the load power management module will give an instruction to control the DC bus to switch from closed circuit to open circuit to protect other equipment. After determining whether the errors of the equipment on board is eliminated, the load power management system performs automatic system reset procedure. As such, the DC bus can be converted from an open circuit to a closed circuit to restart the power supply for the facility.

Abstract: An entity recognition method, apparatus, electronic device, and computer-readable storage medium are provided. The method includes: determining at least one entity boundary word corresponding to a text sequence; determining at least one entity candidate region in the text sequence based on the at least one entity boundary word; and performing entity recognition on the text sequence and identifying at least one entity in the text sequence based on the at least one entity candidate region.

Abstract: The present invention disclosures a recessed structure capable of being conveniently monitored online, wherein comprising a dielectric layer I, and a dielectric layer II positioned above the dielectric layer I, the dielectric layer I comprises a metal via layer and a metal contact layer, the metal contact layer is positioned above the metal via layer; the dielectric layer II comprises an inverted trapezoid groove positioned above the metal contact layer, the inverted trapezoid groove has inclined sidewall, and the horizontal cross-sectional area of the inverted trapezoid groove far away from the metal contact layer is larger than the horizontal cross-sectional area of the inverted trapezoid groove close to the metal contact layer; the inclined sidewall is covered with a reflective film.

Abstract: The present invention disclosures an image sensor structure and a formation method thereof, wherein comprising: a pixel unit array, a peripheral circuit set at the periphery of the pixel unit array, and a composite shield structure around the pixel unit array and between the pixel unit array and the peripheral circuit, the composite shield structure comprises a light shield structure and a heat shield structure; wherein, the light shield structure comprises a metal isolation structure around the pixel unit array for isolating light emitted by the peripheral circuit, and the heat shield structure comprises a cavity set inside the metal isolation structure, the cavity is filled with a thermal isolation medium for preventing heat transfer to the pixel unit array. The present invention can avoid image quality deterioration and distortion caused by light and heat of the peripheral circuit of the image sensor.

Abstract: The present disclosure provides a voltage conversion circuit and a chip. The voltage conversion circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a phase inverter; the source of the first PMOS transistor is connected to an I/O power supply, the drain thereof is connected with a first node, and the gate thereof is connected with a second node; the drain of the first NMOS transistor is connected with the first node, the source thereof is grounded, and the gate thereof is connected to an input signal.

Abstract: A memory and reading, writing and erasing methods thereof. The memory includes: H memory planes arranged in parallel along a first direction, where each memory plane extends in a second direction, and includes M columns of memory strings; each column of memory string extends in a third direction; the first direction, the second direction and the third direction are all different, and H and M are integers greater than zero; each column of memory string includes N rows of memristive memory cells. The memory is also provided with word lines, gating transistors, gating lines, bit lines and a common source line, where memristive memory cells in last rows of all memory strings are connected to the common source line, and the common source line is connected to a reference potential through a reference resistor. Use performance of the memory can be improved.

Abstract: The present invention provides a measurement system and modeling method for radio frequency MOS device modeling. Electrodes that are correspondingly provided in a slave test structure and a master test structure of the measurement system are different, where a source and a drain of a second MOS device are respectively connected to corresponding test ports, and a gate is independently connected out to facilitate setting a corresponding bias voltage. The modeling method configures an initial value of each parasitic element in a subcircuit model by means of a test result of the measurement system, corrects the initial values of at least some parasitic elements, and finally obtains parasitic parameter values of the parasitic elements.

Abstract: A clock circuit comprises an oscillator circuit and a power-on reset circuit, the oscillator circuit comprises a current generating module and a loop oscillation module connected together; the current generating module is used for outputting a control current to the loop oscillation module; the loop oscillation module is used for outputting an oscillation signal with a set frequency under action of the control current; and the power-on reset circuit is connected to the loop oscillation module and is used for providing an enabling control signal to the loop oscillation module after a power supply is powered on to the power-on reset circuit and the oscillator circuit.

Abstract: A razor head includes a frame, elongated blades arranged on an inner side of the frame, and two bridge walls each extending between two points of the frame in an interior of the frame, the bridge walls each including projections arranged in an arrangement direction of the blades. Each of the blades is held between adjacent ones of the projections of the bridge walls. Each of the projections includes a first flat surface and a second flat surface. In each of the bridge walls, the first flat surface and the second flat surface are shifted from each other in a longitudinal direction of the blades so as not to overlap each other, and the first flat surfaces and the second flat surfaces are located on the same position as viewed in the arrangement direction. Each of the projections has a horizontal cross-sectional shape of a parallelogram.

Abstract: The present invention provides a novel process for the preparation of 1-(2-{4-[(4-carbamoyl piperidin-1-yl)methyl]-N-methylbenzamido}ethyl) piperidin-4-yl N-({1, 1?-biphenyl}-2-yl) carbamate of formula (I).