Abstract: A character recognition method includes the following operations: determining that the image of character to be identified corresponds to a matching character of several registered characters according to several vector distances to be identified between a vector of an image of character to be identified and several vectors of several registered character images of several registered characters, and storing a matching vector distance between the vector of the image of character to be identified and a vector of the matching character by a processor; and storing a data of the matching character according to the image of character to be identified when the matching vector distance is less than a vector distance threshold by the processor.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: An inductor device includes a first trace, a second trace, a first capacitor, and at least one connection element. The first trace includes at least two sub-traces. One terminal of the at least two sub-traces is coupled to a first node. The second trace includes at least two sub-traces. One terminal of the at least two sub-traces is coupled to a second node. The first capacitor is coupled between the first node and the second node. The at least one connection element is coupled to another terminal of the at least two sub-traces of the first trace and another terminal of the at least two sub-traces of the second trace, such that the first trace and the second trace form a closed loop.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The Bluetooth host device controls a display device to display a candidate device list, and to display a single device item in the candidate device list to represent the Bluetooth device set, but does not simultaneously display two device items in the candidate device list to represent the first member device and the second member device. The Bluetooth host device generates a first cypher key according to an instruction from the first member device and a device information of the first member device after receiving a selection command. The first member device establishes a connection with the Bluetooth host device, and generates a second cypher key corresponding to the first cypher key according to a device information of the Bluetooth host device.

Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.

Abstract: The present invention provides an image processing circuit including a receiving circuit, a reference value calculating circuit, a center luminance value calculating circuit and an output circuit. In the operations of the image processing circuit, the receiving circuit receives image data. The reference value calculating circuit determines a first reference value and a second reference value corresponding to a plurality of pixels of the image data. The center luminance value calculating circuit refers to the first reference value and the second reference value to generate a center luminance value. The output circuit determines output luminance values of the plurality of pixel values according to the image data, the first reference value and the second reference value.

Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Abstract: The present application provides a circuit design method and an associated circuit. The circuit design method is for generating a circuit, and the method includes: arranging a plurality of attack detection circuits around a specific circuit unit, wherein the specific circuit unit is in the circuit; determining a number of a plurality of spare cells required by the circuit according to a number of the attack detection circuit; and placing the spare cells in the circuit according to the number of the spare cells.

Abstract: An inductor device includes an 8-shaped inductor structure, a first spiral wire, a first connector, a second connector, and a first interlaced component. The 8-shaped inductor structure includes two first-wires and two second-wires. The first spiral wire is disposed on an inner side of the two first-wires. The first connector is coupled to one of the two first-wires and one of the two second-wires. The second connector is coupled to another one of the two first-wires. The first interlaced component is coupled to the first spiral wire and another one of the two second-wires, and the first interlaced component is coupled to the first connector and the second connector in an interlaced manner respectively.

Abstract: An integrated inductor is provided. The integrated inductor includes a first winding and a second winding, and has a first end, a second end, and a node. The first winding utilizes the first end and the node as two ends thereof and includes a first coil and a second coil, which do not overlap. The second winding utilizes the second end and the node as two ends thereof and includes a third coil and a fourth coil, which do not overlap. The first coil and the third coil have an overlapping area, and the second coil and the fourth coil have an overlapping area. The first coil is surrounded by the third coil, and the fourth coil is surrounded by the second coil.

Abstract: A processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a first load instruction included in a plurality of load instructions to generate a first decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instructions use a same register. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the first load instruction according to the first decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instructions use the same register, the data buffer is configured to store the first address generated from the address generator, and store data requested by the first load instruction according to the first address.

Abstract: A method and apparatus for simulating breakdown of an electronic component are provided. The method includes: when a terminal of an equivalent circuit model receives test charges, pulling up a voltage level of a first node of the equivalent circuit model; when the voltage level of the first node reaches a first threshold, turning on a first voltage controlled switch to pull up a voltage level of a second node of the equivalent circuit model; when the voltage level of the second mode reaches a second threshold, turning on a second voltage controlled switch to pull down a voltage level of the terminal to a holding voltage level to simulate snapback breakdown of the electronic component; and turning on a third voltage controlled switch to pull down the voltage level of the second node to turn off the second voltage controlled switch, thereby simulating second breakdown of the electronic component.

Abstract: A signal compensation device includes a first receiving circuit, a second receiving circuit, a first buffer, a second buffer, a third buffer, and a processing circuit. The first receiving circuit receives a first video signal from a first video source. The second receiving circuit receives a second video signal from a second video source, wherein both the first video signal and the second video signal correspond to a same program. The first buffer stores a first transport stream (TS) packet group corresponding to the first video signal. The second buffer stores a second TS packet group corresponding to the second video signal. The processing circuit dynamically stores a first TS packet of the first TS packet group or a second TS packet of the second TS packet group to the third buffer according to a predetermined source in response to TS packet status.

Abstract: A neural network system and an operation method for a neural network system are provided. The neural network system includes at least one edge device and a server. Each edge device stores a neural network architecture. The neural network architecture includes at least one operator and a model identifier, and the at least one operator of the neural network architecture stored in the each edge device includes an operator identifier. The server is connected to the each edge device. The each edge device is configured to, upon being powered on, transmit the operator identifier of each operator to the server to request the server to return parameters for the each operator; receive the parameters of the each operator and combine the parameters of the each operator with the neural network architecture to obtain a neural network model; and execute a predetermined task based on the neural network model.

Abstract: The present application provides a method for a WiFi module and system of the same. The method including: determining whether a specific process is a high-power consumption event; and when the specific process is determined as the high-power consumption event, performing a time-divisional operation upon the specific process. The present application further provides another method for a WiFi module, including: determining whether a specific process is a high-power consumption event; and when the specific process is determined as the high-power consumption event, estimating a first power consumption request information and transmitting the information to a control module of a local end; and receiving a first response corresponding to the first power consumption request information from the control module.

Abstract: A method for retrieving a program data and a circuit system thereof are provided. The method that uses a dynamic packet identifier (PID) filter to retrieve the program data can be applied to a digital TV system. In the method, a master guide table is retrieved from a transport stream of digital TV signals, and a parsing method is executed to obtain a series of the PIDs. A polling method is used to obtain the program data corresponding to each of the PIDs. A filter window is applied to scan the PIDs for polling the program data corresponding to each of a group of the PIDs at once. After that, the filter window is shifted to a next group of the PIDs for polling the program data with respect to each of the PIDs, and an electronic program guide is accordingly formed.

Abstract: A multi-member Bluetooth device for communicating data with a remote Bluetooth device is disclosed including: a main Bluetooth circuit and an auxiliary Bluetooth circuit. In the period during which the auxiliary Bluetooth circuit operates at a relay mode, the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device and forwards the received packets to the auxiliary Bluetooth circuit; the auxiliary Bluetooth circuit does not sniff packets issued from the remote Bluetooth device, but will switch to a sniffing mode if a signal reception quality indicator of the auxiliary Bluetooth circuit is superior to a predetermined indicator value. In the period during which the auxiliary Bluetooth circuit operates at the sniffing mode, the auxiliary Bluetooth circuit sniffs packets issued from the remote Bluetooth device and the main Bluetooth circuit receives packets transmitted from the remote Bluetooth device.

Abstract: An image processing method applied to a display device having a processing circuit and a screen and includes: receiving a first image from one of a plurality of electronic devices; detecting whether the first image has a black border area; and if the first image has the black border area, performing a first display operation, wherein performing the first display operation includes: removing the black border area of the first image, to generate a second image; adjusting the size of the second image according to the size of a display area of the screen; calculating a first blank area of the screen based on the adjusted second image; requesting a third image from another one of the electronic devices according to the size of the first blank area; and filling the display area of the screen with the adjusted second image and the third image.

Abstract: A semiconductor device includes a first coil, a second coil, and a third coil. The second coil is disposed with respect to the first coil. The third coil is configured to sense a signal on the first coil. A first overlapped area, on a projection plane, of the third coil and the first coil is larger than a second overlapped area, on the projection plane, of the third coil and the second coil.

Abstract: An amplifier includes an amplifier circuit and a gain adjusting circuit. The amplifier circuit has a design gain and a real gain and is configured to output an output signal according to an input signal and the real gain. The gain adjusting circuit is coupled to the amplifier circuit and is configured to receive the input signal to compare a voltage of the input signal with a first reference voltage, wherein when the voltage of the input signal exceeds the first reference voltage, the gain adjusting circuit increases the real gain of the amplifier circuit, so that the real gain approach the design gain.