Abstract: A player device includes a multi-media receiving device and a signal processing device. The signal processing device performs a mixing operation to mix a multi-media signal and a pseudo stereo signal to generate a mixed multi-media signal. The signal processing device further converts a system sound from a mono sound signal into the pseudo stereo signal by selecting at least one frequency component of the system sound as a modulation signal and combining a delayed version of the modulation signal and remaining frequency components of the system sound to generate the pseudo stereo signal. In the mixing operation, the signal processing device combines a multi-media sound component of a first channel and a system sound component of the first channel and combines a multi-media sound component of a second channel and a system sound component of the second channel to generate the mixed multimedia signal.

Abstract: A network packet processing method includes: by a processor of the network device, generating a first predetermined packet, and providing the first predetermined packet to a core circuit of a network device; by a packet parser of the core circuit, parsing the first predetermined packet to obtain a first parsing result corresponding to the first predetermined packet, generating a control information corresponding to the first predetermined packet according to the first parsing result, and providing the first predetermined packet and the control information to a front-end processing circuit; and by the front-end processing circuit, obtaining a first transmitting timestamp corresponding to the first predetermined packet in response to reception of the first predetermined packet, determining to write the first transmitting timestamp into the first predetermined packet or a register according to the control information, and transmitting the first predetermined packet.

Abstract: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably couple with an MDI circuit to conduct data communication with a respondent-side circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit.

Abstract: An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably conduct data communication with a respondent-side circuit through an MDI circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.

Abstract: An integrated stack transformer is provided, wherein the integrated stack transformer includes a first winding, a second winding and a third winding implemented by a first metal layer, and a fourth winding and a fifth winding implemented by a second metal layer. The second winding is positioned between the first winding and the third winding, the fourth winding substantially overlaps the first winding, the fifth winding substantially overlaps the third winding, and a distance between the fifth winding and the fourth winding is less than a distance between the third winding and the first winding. The first winding, the third winding, the fourth winding and the fifth winding form a part of one of a primary inductor and a secondary inductor of the integrated stack transformer, and the second winding is a part of the other of the primary inductor and the secondary inductor.

Abstract: A data accessing method includes providing a first memory including a plurality of memory pages, acquiring a usage order value of each memory page of the plurality of memory pages, acquiring a first usage order value having a highest priority from a plurality of usage order values corresponding to the plurality of memory pages in the first memory, updating the first memory after a first memory page having the first usage order value is used, acquiring a second usage order value having a highest priority from the updated first memory after the first memory is updated, and using a second memory page having the second usage order.

Abstract: A storage device includes a controller and a memory. A method of storage space management for the storage device is executed to perform steps as below. The controller calculates an expectedly used capacity and an effective capacity of the memory. The controller determines whether blocks of the memory include one or more blocks that are non-bad blocks and are prohibited from reading/writing. When the one or more blocks are determined to be non-bad blocks and to be prohibited from reading/writing, the controller marks each of the one or more blocks as a restricted block other than a bad block, thereby maintaining the effective capacity to be unchanged. The controller compares difference of the effective capacity and a total capacity of the one or more blocks that are marked as the restricted block to the expectedly used capacity to determine whether to prohibit programming to the memory.

Abstract: A content addressable memory cell includes storage circuits and a comparator circuit. A first storage circuit of the storage circuits is configured to store data, and a second storage circuit of the storage circuits is configured to store a state bit. The comparator circuit is configured to determine whether to adjust a level of a match line to a level of one of the data and the state bit in response to levels of search bit lines and another one of the data and the state bit.

Abstract: The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least ?P?.

Abstract: An embedded system includes a host controller circuit and a microcontroller circuit. The host controller circuit is configured to access a storage device to obtain an address of a first firmware file in the storage device. The microcontroller circuit is configured to determine whether a memory circuit is being accessed by other circuits, in which the memory circuit includes memory blocks. If the memory circuit is not being accessed by the other circuits, the microcontroller circuit is further to control the host controller circuit to write the first firmware file to a first block of the memory blocks according to the address.

Abstract: A bootstrapped switch includes a sampling transistor, a bootstrapped circuit, and a buffer circuit. The sampling transistor is configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, in which a body of the sampling transistor is configured to receive a buffer signal. The bootstrapped circuit is configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor. The buffer circuit is configured to generate the buffer signal according to the input signal.

Abstract: An audio processing device includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.

Abstract: The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.

Abstract: A resistive attenuator and a method for improving linearity of the resistive attenuator are provided. The resistive attenuator includes a first transistor, an attenuation circuit and a compensation circuit, wherein both the first transistor and the attenuation circuit are coupled between an input terminal and an output terminal of the resistive attenuator, and the compensation circuit is coupled to the first transistor. The first transistor is configured to provide a first signal path between the input terminal and the output terminal. The attenuation circuit is configured to provide a second signal path between the input terminal and the output terminal, wherein signal attenuation of the second signal path is greater than signal attenuation of the first signal path. The compensation circuit is configured to compensate nonlinear distortion caused by the first transistor.

Abstract: A chip includes a first circuit under test, a second circuit under test, and a clock masking circuit. The first circuit under test is coupled to the second circuit under test. The clock masking circuit includes a first clock control circuit, a second clock control circuit, and an enabling circuit. The first clock control circuit is configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal. The second clock control circuit is configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal. The enabling circuit is configured to provide a first enable signal for the first clock control circuit and a second enable signal for the second clock control circuit.

Abstract: A circuit for preventing current backflow includes: a signal connection terminal, a power input terminal, an internal power supply terminal, an electrostatic protection circuit, a first switch element and a cut-off control circuit. The electrostatic protection circuit is coupled to the signal connection terminal and the internal power supply terminal. The first switch element is coupled between the power input terminal and the internal power supply terminal. The cut-off control circuit is coupled to the signal connection terminal, the power input terminal and the first switch element. The cut-off control circuit controls the switching of the first switch element according to a voltage of the signal connection terminal and a voltage of the power input terminal.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device transmits a device information of the first member device to the Bluetooth host device. The Bluetooth host device controls a display device to display a candidate device list, and to display a single device item in the candidate device list to represent the Bluetooth device set, but does not simultaneously display two device items in the candidate device list to represent the first member device and the second member device. The Bluetooth host device further establishes a connection with the first member device to conduct pairing procedure to generate a first cypher key after receiving a selection command. The first member device further establishes a connection with the Bluetooth host device to conduct pairing procedure to generate a second cypher key.

Abstract: A dongle coupled between a power supplying device for supplying power and a power receiving device for receiving power includes a downstream facing port (DFP), an upstream facing port (UFP) and a controller. The controller is arranged to control deliveries of the power and messages between the power supplying device and the power receiving device. In response to a first power request message received from the power receiving device, the controller is arranged to determine whether a power type request by the power receiving device is Programmable Power Supply (PPS) according to the first power request message. When determining that the power type request by the power receiving device is PPS, the controller is arranged to start first waiting timer, and when the first waiting timer expires, the controller is arranged to send a request accept message to the power receiving device through the UFP.

Abstract: An image display system includes a display device, a second memory circuit, and an image processor circuit. The display device includes a panel and a first memory circuit, in which the first memory circuit is configured to store first predetermined data for controlling the panel. The second memory circuit is configured to store second predetermined data. The image processor circuit is configured to read first part data in the first predetermined data and second part data in the second predetermined data and compare the first part data with the second part data. If the first part data is identical to the second part data, the image processor circuit is further configured to output a driving signal according to the second predetermined data to control the panel to start displaying an image.

Abstract: A super resolution image generating device capable of processing an image flexibly includes a scaling-up circuit, a front-end circuit, a first branch circuit, a second branch circuit, and an arithmetic circuit. The scaling-up circuit scales up the image to generate an enlarged image including N pixel values. The front-end circuit extracts features of the image to generate a front-end feature map. The first branch circuit extracts features of the front-end feature map to generate a first feature map, and scales up the first feature map to generate N first values. The second branch circuit processes the front-end feature map to generate a second feature map, scales up the second feature map to generate N second values, and processes the N second values to generate N processed values. The arithmetic circuit combines the N pixel values, the N first values, and the N processed values to generate a super resolution image.