Abstract: A semiconductor chip includes a first electrode connected to a gate of a power device, a second electrode connected to an emitter or a source of the power device, a third electrode, and a gate protection element. The gate protection element includes a first node and a second node, and a plurality of stages of p-n junctions formed between the first node and the second node. When one of the first electrode and the second electrode is a target electrode and the other is a non-target electrode, and the first node is connected to the third electrode and the second node is connected to the target electrode. Then, the first electrode, the second electrode, the third electrode and the gate protection element are formed in the same semiconductor chip.

Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.

Abstract: An occupied area of the switch circuit electrically connected to a memory cell is reduced to reduce the size of a semiconductor device. A semiconductor device according to an embodiment includes a memory cell on a semiconductor substrate and a semiconductor chip in which a switch circuit electrically connected to the memory cell is formed, wherein the switch circuit includes a second transistor electrically connected to the memory cell, and the second transistor includes a second word gate formed on the semiconductor substrate through a third gate insulating film, and a second coupling gate formed on the semiconductor substrate through a fourth gate insulating film having a thickness greater than that of the third gate insulating film, wherein a voltage higher than a voltage applied to the second word gate is applied to the second coupling gate of the second transistor when a current is applied to the memory cell.

Abstract: A data processing device that can monitor properly the state of the interrupt processing of a virtual machine is provided. The data processing device according to an aspect of the present disclosure includes an arithmetic unit that executes multiple virtual machines, respectively, and an interrupt controller that instructs execution of the interrupt processing to the arithmetic unit with the virtual machine information to specify at least one of the multiple virtual machines. The interrupt controller includes a counter to count the number of interrupts for each virtual machine based on the virtual machine information.

Abstract: A first MISFET is formed on a semiconductor layer of an SOI substrate in a circuit region and a second MISFET composing a TEG for VC inspection is formed on the semiconductor layer of the SOI substrate in a TEG region. An interlayer insulating film is formed, contact holes are formed in the interlayer insulating film, and plugs are formed in the contact holes, respectively. In the TEG region, the plugs include a plug electrically connected to both the semiconductor substrate composing the SOI substrate and the semiconductor layer composing the SOI substrate.

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Abstract: Semiconductor device includes a controller for controlling a charging of a battery cell. When the battery cell is charged, the controller generates a voltage command value which instructs to a charger so that an upper limit value of an output voltage output from the charger is higher than a predetermined voltage which is a maximum potential voltage that the battery cell can be charged maximally.

Abstract: A debug apparatus for performing allocation of target programs in which temperature is uniformized is provided. The debug apparatus receives temperature data measured by temperature sensors from a semiconductor device. The debug apparatus determines, as an analysis result of the temperature data, a CPU where the number of target programs executed is to be decreased and a CPU where the number of target programs executed is to be increased. The debug apparatus changes allocation of the target programs executed by a plurality of CPUs in the semiconductor device based on the analysis result of the temperature data.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.

Abstract: A semiconductor device has a semiconductor chip having a plurality of pads and wires electrically connected to the plurality of pads, respectively. The plurality of pads includes a plurality of first pads which is electrically connected to a circuit included in the semiconductor chip and to which first wires are bonded and a second pad which is an electrode pad for wire connection test and to which a second wire is bonded.

Abstract: A semiconductor device, a battery pack, a method of controlling the semiconductor device, and a control program capable of accurately measuring a remaining capacity of a battery is provided. The semiconductor device includes: a current measurement circuit configured to measure a current value of a first current supplied from a battery to the semiconductor device that is a host device and a current value of a second current supplied from the battery to a load; and a computing circuit configured to calculate the remaining capacity of the battery, based on an accumulation value of the first current and an accumulation value of the second current in a period from start of discharging to end of discharging in the battery.

Abstract: A CAN communication controller and a method of operating a CAN communication controller are disclosed. The CAN communication controller is for transmitting first and second types of frames wherein the first type of frame is used to transmit event-triggered communication data and the second type of frame is used to transmit best effort traffic data, the CAN communication controller configured, in response to transmitting a frame of the second type having a given identifier, to delay arbitration of a following frame of the second type having the given identifier, and not to delay arbitration of a frame of the first type.

Abstract: A differential amplifier includes a first differential amplifier circuit as a first stage, a second differential amplifier circuit having a common mode feedback circuit in a second stage, and a feedback differential circuit configured to multiply a differential signal between a differential output of the first differential amplifier circuit and a differential input of the second differential amplifier circuit by a magnitude of a differential output of the common mode feedback circuit.

Abstract: A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

Abstract: A semiconductor device which is a processor includes a plurality of first power supply regions in each of which a functional module having a predetermined function is arranged and to which a power supply voltage is individually supplied, a setting unit configured to specify an order of supplying the power supply voltage in the plurality of first power supply regions, and a power controller configured to supply the power supply voltage to the plurality of first power supply regions in accordance with the order specified by the setting unit.

Abstract: A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.

Abstract: Example implementations includes a method of partitioning a non-transitory memory device by detecting a boot state of a processing device including a non-transitory memory device, identifying a startup state of the processing device based on the boot state, and partitioning the memory device into at least one secure address region, in accordance with a determination that the startup state satisfies an operating state condition. Example implementations also include a method of generating a secure partition associated with a non-transitory memory device by identifying a target processing instruction restricted to execution at a secure subsystem of a processing device, assigning to the target processing instruction a secure address, associating the secure address with a secure address region of a non-transitory memory device of the processing device, and generating a secure partition table including the secure address.

Abstract: A resolver converter includes a tracking loop circuit that calculates an angle ? from a resolver output signal, a control and diagnosis circuit that controls the tracking loop circuit and diagnoses based on the resolver output signal, wherein the control and diagnosis circuit, by operating the tracking loop circuit as a direct digital synthesizer (DDS), synchronously detects a noise signal superimposed on the resolver output signal.

Abstract: A semiconductor device includes a crystal oscillator circuit, a first noise application circuit, and a second noise application circuit. The first noise application circuit is connected to the crystal oscillator circuit and is configured to drive a crystal resonator by selectively applying initial noises of opposite phases to a first external terminal and a second external terminal. The second noise application circuit applies a second noise to the first external terminal by amplifying a signal at the first external terminal and returning the amplified signal to the first external terminal, thereby driving an oscillation amplifier and a crystal resonator of the crystal oscillator circuit and shortening a start-up time of the crystal oscillator circuit.

Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.