Patents Assigned to Renesas Electronic Corporation
  • Patent number: 11966718
    Abstract: Placement of bridges connecting CAE tools and virtual ECU simulation tools is facilitated. A virtual developmental environment apparatus includes a processing execution unit and a memory for storing a MILS model including a controller block and a plant block, first setting information, a program for realizing a function in the controller block used in executing simulation of the virtual ECU, and second setting information. The processing execution unit identifies a controller block in the MILS model based on the first setting information, arranges a bridge for connecting the input port and the output port and the I/O port of the virtual ECU to the input port and the output port of the identified controller block, and connects the bridge and the I/O port of the virtual ECU based on the second setting information.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: April 23, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Mitsugu Inoue, Koichi Sato
  • Patent number: 11961909
    Abstract: Semiconductor device includes a well region formed in an active region of a semiconductor substrate, a gate electrode formed on the well region via a gate dielectric film, and a source region and a drain region formed in the well region. At the vicinity of both end portions of the active region in the first direction, a first region and a second region having the same conductivity type as the well region and having impurity concentration higher than that of the well region are formed in the well region. The first region and the second region are spaced from each other in a second direction perpendicular to the first direction, and at least a portion of each of them is located under the gate electrode. The first region and the second region are not formed at the center portion of the active region in the first direction.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: April 16, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Sugiyama
  • Patent number: 11955101
    Abstract: A display control device and a display control method capable of displaying a desired image regardless of a state of wireless communication are provided. A wireless control unit causes an external apparatus to draw a first image in accordance with input information. A first unit acquires the first image via the wireless communication and displays the first image on a display apparatus. A second unit causes a GPU to draw a second image in accordance with the unput information and displays the second image on the display apparatus. A switching unit determines whether a received radio wave is in a good state or a bad state, select the first unit when a determination result is that the received radio wave is in the good state, and select the second unit when the determination result is that the received radio wave is in the bad state.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 9, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshihito Ogawa
  • Patent number: 11948916
    Abstract: The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: April 2, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shuuichi Kariyazaki
  • Patent number: 11949358
    Abstract: A control circuit receives a command from outside and causes an arithmetic unit to perform arithmetic operation M times (M is an integer of 2 or more) by using input data from outside and calculated data held in a memory, thereby making the arithmetic unit and the memory function as an IIR filter. The IIR filter is a filter capable of determining output data by arithmetic operation of K times out of the M times (K<M). The control circuit receives the command from outside and then causes the arithmetic unit to perform the arithmetic operation K times in advance, thereby determining the output data and outputting the output data to outside at that time.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: April 2, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takeshi Nitta
  • Patent number: 11949412
    Abstract: A semiconductor device includes a galvanic isolator; a transmitting circuit that transmits a transmission signal via the galvanic isolator; a receiving circuit that receives a received signal corresponding to the transmission signal via the galvanic isolator; an encoding circuit that encodes two input signals and generates the transmission signal; and a decoding circuit that decodes the two input signals from the received signals.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: April 2, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunichi Kaeriyama
  • Patent number: 11942163
    Abstract: In a case of achievement of a neural network circuit using a plurality of nonvolatile memory cells, a technique capable of accurately reading information recorded in the plurality of nonvolatile memory cells is provided. A semiconductor device includes: a plurality of nonvolatile memory cells; a plurality of reference-current cells; and a sense amplifier comparing an electric current flowing in each of the plurality of nonvolatile memory cells and an electric current flowing in each of the plurality of reference-current cells. In this case, each cross-sectional structure of the plurality of reference-current cells is the same as each cross-sectional structure of the plurality of nonvolatile memory cells. The writing operation or the erasing operation is also performed to each of the plurality of reference-current memory cells when the writing operation or the erasing operation is performed to each of the plurality of nonvolatile memory cells.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: March 26, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiyuki Kawashima
  • Patent number: 11942890
    Abstract: The magnetic pole position of the rotor is estimated with high accuracy at the initial start of a three-phase motor of the sensorless system. Semiconductor device for driving and controlling the three-phase motor of the sensorless system have a detector connected to the three-phase output nodes of the inverter circuit and the virtual neutral point (or neutral point), and detecting a voltage generated in the output node of the non-energized phase of the three-phase. Controller applies the initial drive voltage by the inverter circuit to any two phases of the three-phase motor based on the estimated position of the magnetic pole of the rotor in the stop state. Controller estimates the position of the rotor based on a difference voltage detected by the detector in a driving voltage applying period and a regeneration period immediately after or immediately before the driving voltage applying period.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: March 26, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Narumi, Minoru Kurosawa, Takeshi Ohtsuki
  • Patent number: 11942471
    Abstract: A semiconductor chip includes a first electrode connected to a gate of a power device, a second electrode connected to an emitter or a source of the power device, a third electrode, and a gate protection element. The gate protection element includes a first node and a second node, and a plurality of stages of p-n junctions formed between the first node and the second node. When one of the first electrode and the second electrode is a target electrode and the other is a non-target electrode, and the first node is connected to the third electrode and the second node is connected to the target electrode. Then, the first electrode, the second electrode, the third electrode and the gate protection element are formed in the same semiconductor chip.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 26, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshito Tanaka, Hideaki Hashimoto
  • Patent number: 11925025
    Abstract: An occupied area of the switch circuit electrically connected to a memory cell is reduced to reduce the size of a semiconductor device. A semiconductor device according to an embodiment includes a memory cell on a semiconductor substrate and a semiconductor chip in which a switch circuit electrically connected to the memory cell is formed, wherein the switch circuit includes a second transistor electrically connected to the memory cell, and the second transistor includes a second word gate formed on the semiconductor substrate through a third gate insulating film, and a second coupling gate formed on the semiconductor substrate through a fourth gate insulating film having a thickness greater than that of the third gate insulating film, wherein a voltage higher than a voltage applied to the second word gate is applied to the second coupling gate of the second transistor when a current is applied to the memory cell.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 5, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Junichi Suzuki
  • Patent number: 11923296
    Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: March 5, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naohito Suzumura, Kenichiro Sonoda, Hideaki Tsuchiya
  • Patent number: 11915032
    Abstract: A data processing device that can monitor properly the state of the interrupt processing of a virtual machine is provided. The data processing device according to an aspect of the present disclosure includes an arithmetic unit that executes multiple virtual machines, respectively, and an interrupt controller that instructs execution of the interrupt processing to the arithmetic unit with the virtual machine information to specify at least one of the multiple virtual machines. The interrupt controller includes a counter to count the number of interrupts for each virtual machine based on the virtual machine information.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 27, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuhiro Sugita
  • Patent number: 11915975
    Abstract: A first MISFET is formed on a semiconductor layer of an SOI substrate in a circuit region and a second MISFET composing a TEG for VC inspection is formed on the semiconductor layer of the SOI substrate in a TEG region. An interlayer insulating film is formed, contact holes are formed in the interlayer insulating film, and plugs are formed in the contact holes, respectively. In the TEG region, the plugs include a plug electrically connected to both the semiconductor substrate composing the SOI substrate and the semiconductor layer composing the SOI substrate.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: February 27, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Yoshida, Tomohiro Tomizawa
  • Patent number: 11907681
    Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: February 20, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa
  • Patent number: 11909247
    Abstract: Semiconductor device includes a controller for controlling a charging of a battery cell. When the battery cell is charged, the controller generates a voltage command value which instructs to a charger so that an upper limit value of an output voltage output from the charger is higher than a predetermined voltage which is a maximum potential voltage that the battery cell can be charged maximally.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: February 20, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Uchinohae, Youhei Kengoyama
  • Patent number: 11899564
    Abstract: A debug apparatus for performing allocation of target programs in which temperature is uniformized is provided. The debug apparatus receives temperature data measured by temperature sensors from a semiconductor device. The debug apparatus determines, as an analysis result of the temperature data, a CPU where the number of target programs executed is to be decreased and a CPU where the number of target programs executed is to be increased. The debug apparatus changes allocation of the target programs executed by a plurality of CPUs in the semiconductor device based on the analysis result of the temperature data.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: February 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoyoshi Ujii, Yuki Mori, Kazunori Ochiai
  • Patent number: 11901288
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba, Shinichi Uchida
  • Patent number: 11901298
    Abstract: A semiconductor device has a semiconductor chip having a plurality of pads and wires electrically connected to the plurality of pads, respectively. The plurality of pads includes a plurality of first pads which is electrically connected to a circuit included in the semiconductor chip and to which first wires are bonded and a second pad which is an electrode pad for wire connection test and to which a second wire is bonded.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: February 13, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kenji Ikura
  • Publication number: 20240044990
    Abstract: A semiconductor device, a battery pack, a method of controlling the semiconductor device, and a control program capable of accurately measuring a remaining capacity of a battery is provided. The semiconductor device includes: a current measurement circuit configured to measure a current value of a first current supplied from a battery to the semiconductor device that is a host device and a current value of a second current supplied from the battery to a load; and a computing circuit configured to calculate the remaining capacity of the battery, based on an accumulation value of the first current and an accumulation value of the second current in a period from start of discharging to end of discharging in the battery.
    Type: Application
    Filed: July 26, 2023
    Publication date: February 8, 2024
    Applicant: Renesas Electronics Corporation
    Inventor: Gen NAGASHIMA
  • Publication number: 20240039756
    Abstract: A CAN communication controller and a method of operating a CAN communication controller are disclosed. The CAN communication controller is for transmitting first and second types of frames wherein the first type of frame is used to transmit event-triggered communication data and the second type of frame is used to transmit best effort traffic data, the CAN communication controller configured, in response to transmitting a frame of the second type having a given identifier, to delay arbitration of a following frame of the second type having the given identifier, and not to delay arbitration of a frame of the first type.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 1, 2024
    Applicant: Renesas Electronics Corporation
    Inventors: Christian MARDMÖLLER, Tobias BELITZ