Abstract: The plurality of CAM cells MC are configured to discriminate a match or mismatch between stored data stored in advance and search data. A match line is coupled to a plurality of CAM cells, and has a voltage level controlled based on discrimination results of the plurality of CAM cells. A first transistor and a second transistor are coupled in series between a common match output line and a predetermined power source. The first transistor is controlled to be turned ON or OFF based on a voltage level of the match line, and the second transistor is controlled to be turned ON or OFF by a search enabling signal asserted at the time of a search operation.

Abstract: A network device comprising a set of queues and a time-aware shaper which comprises a set of transmission gates and gate control instructions. The gate control list comprises a set of individual gate control lists, each individual gate control list configured to control a respective gate and which comprises a sequence of entries, each entry comprising a duration of time.

Abstract: A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

Abstract: A semiconductor device includes: a semiconductor substrate; an insulating layer formed on the semiconductor substrate; an optical waveguide formed on the insulating layer, extending in a first direction in a plan view, and being made of silicon; and an interlayer insulating film formed on the insulating layer to cover the optical waveguide. In this case, a crystal surface of a side surface of the optical waveguide is a (111) surface.

Abstract: Improving a reliability of a semiconductor device. A resistive element is comprised of a semiconductor layer of the SOI substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer EP has two semiconductor portions formed on the semiconductor layer and spaced apart from each other. The semiconductor layer has a region on where one of the semiconductor portion is formed, a region on where another of the semiconductor portion is formed, and a region on where the epitaxial semiconductor layer is not formed.

Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 ?m.

Abstract: Detection transistor MNd flows a detection current IdN to a current path CP1n when an output voltage Vo generated in a load terminal PN1 is than a ground voltage GND. A current mirror circuit CMp1 transfers the detection current IdN flowing in the current path CP1n to a current path CP2a. Detecting resistor element Rd1 converts a mirror current I2a flowing in the current path CP2a to a detection voltage Vd1. A control transistor MNc1 is turned on when the converted detection voltage Vd1 is higher than a predetermined value. Then, the output transistor QO is controlled to be off while the control transistor MNc1 is on.

Abstract: A semiconductor device and a method for controlling body bias thereof capable of properly controlling body bias of a transistor even in a case where process variation occurs are provided. Operation speeds of ring oscillators ROSCn and ROSCp respectively change due to an influence of process variation at an NMOS transistor MN side and a PMOS transistor MP side. Speed/bias data represent a correspondence relationship between the operation speeds of the ring oscillators ROSCn and ROSCp and set values V1n and V1p of body biases VBN and VBP. A body bias controller receives speed values Sn and Sp measured for the ring oscillators ROSCn and ROSCp to which the body biases VBN and VBP based on default values are respectively applied, and obtains the set values V1n and V1p on the basis of the speed/bias data.

Abstract: An image sensor including an ADC circuit receiving pixel data to be supplied in parallel from the a pixel array, outputting a reference signal in accordance with a digital code, comparing the reference signal and the pixel data, and outputting the digital code at which the reference signal and the pixel data have a predetermined relation, the ADC circuit including a ramp-signal generating circuit outputting a ramp signal having a gradient with respect to change of the digital code, the gradient being different between when the digital code is in a first range and when the digital code is in a second range different from the first range and an attenuator receiving the ramp signal to be supplied and outputting the reference signal having a gradient being the same between when the digital code is in the first range and when the digital code is in the second range.

Abstract: Example implementations include a system of secure decryption by virtualization and translation of physical encryption keys, the system having a key translation memory operable to store at least one physical mapping address corresponding to at least one virtual key address, a physical key memory operable to store at least one physical encryption key at a physical memory address thereof; and a key security engine operable generate at least one key address translation index, obtain, from the key translation memory, the physical mapping address based on the key address translation index and the virtual key address, and retrieve, from the physical key memory, the physical encryption key stored at the physical memory address.

Abstract: A conventional network managing method has a problem that there is a high possibility that a setting error of communication software occurs. According to one embodiment, a non-transitory computer-readable medium including a network managing program is executed in a master apparatus, system information stored in a slave apparatus in advance is read out in a procedure conforming to an SNMP, protocol information in which a communication protocol that can be used by the slave apparatus is described is read out from the slave apparatus by using an object ID described in the system information thus read out, and the protocol information thus read out is referred to start communication with the slave apparatus by executing software corresponding to the communication protocol.

Abstract: Systems and methods for evaluating a set of bounding boxes in a blended image are described. A system can include an integrated circuit configured to obtain expected bounding box data. The expected bounding box data can be based on coordinates data of an image. The integrated circuit can determine target coordinates based on the expected bounding box data. The integrated circuit can receive a blended image including a set of objects and a set of bounding boxes. The integrated circuit can extract pixel values located at the target coordinates in the blended image. The integrated circuit can identify an error relating to the set of bounding boxes based on the extracted pixel values and the expected bounding box data.

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

Abstract: To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.

Abstract: A semiconductor device includes a semiconductor substrate having first and second surfaces, an insulated gate bipolar transistor (IGBT) and a diode formed on the semiconductor substrate, wherein the diode comprises a drift layer of a first conductivity type formed so as to have a first region on the first surface of the semiconductor substrate, a first body layer of a second conductivity type formed so as to have a second region adjacent to the first region at an upper portion of the drift layer, a first floating layer of the second conductivity type formed so as to have a third region adjacent to the first region at an upper portion of the drift layer, a first trench electrode formed in a region adjacent to the first floating layer at an upper portion of the drift layer, and a first control gate formed on top of the first region.

Abstract: Controllers are provided for providing ports corresponding to Dual Role Powers (DRPs), which may be both the feed side and the receive side, in accordance with the USB Type-C and/or USB Power Delivery standards. The controller includes a control interface for controlling a power management unit for controlling charging and discharging of the secondary battery, a signal transmission module for exchanging a signal with a connection destination via a communication line in the USB cable, and a sequence execution unit. If the power supply from the secondary battery becomes over discharged while the power stored in the secondary battery as the power supply side is being supplied to the connection destination, the sequence execution unit stops the substantial execution of the sequence as the power receiving side unless a predetermined condition is satisfied.

Abstract: A Semiconductor device includes an insulating layer, an optical waveguide, a first dummy semiconductor film, a second semiconductor film and a third semiconductor film. The optical waveguide is formed on the insulating layer. The first dummy semiconductor film is formed on the insulating layer and is spaced apart from the optical waveguide. The first dummy semiconductor film is formed on the first semiconductor film. The second semiconductor film is integrally formed with the optical waveguide as a single member on the insulating layer. The third semiconductor film is formed on the second semiconductor film. A material of the first dummy semiconductor film is different from a material of the optical waveguide. In plan view, a distance between the optical waveguide and the first dummy semiconductor film in a first direction perpendicular to an extending direction of the optical waveguide is greater than a thickness of the insulating layer.

Abstract: The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.

Abstract: The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.