Patents Assigned to Renesas Electronic Corporation
  • Publication number: 20240039492
    Abstract: A differential amplifier includes a first differential amplifier circuit as a first stage, a second differential amplifier circuit having a common mode feedback circuit in a second stage, and a feedback differential circuit configured to multiply a differential signal between a differential output of the first differential amplifier circuit and a differential input of the second differential amplifier circuit by a magnitude of a differential output of the common mode feedback circuit.
    Type: Application
    Filed: July 26, 2023
    Publication date: February 1, 2024
    Applicant: Renesas Electronics Corporation
    Inventor: Nobuyuki MORIKOSHI
  • Patent number: 11887935
    Abstract: A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: January 30, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 11886271
    Abstract: A semiconductor device which is a processor includes a plurality of first power supply regions in each of which a functional module having a predetermined function is arranged and to which a power supply voltage is individually supplied, a setting unit configured to specify an order of supplying the power supply voltage in the plurality of first power supply regions, and a power controller configured to supply the power supply voltage to the plurality of first power supply regions in accordance with the order specified by the setting unit.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: January 30, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takayoshi Shiraishi, Tomohiro Katayama
  • Patent number: 11882697
    Abstract: A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: January 23, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shu Shimizu
  • Patent number: 11880718
    Abstract: Example implementations includes a method of partitioning a non-transitory memory device by detecting a boot state of a processing device including a non-transitory memory device, identifying a startup state of the processing device based on the boot state, and partitioning the memory device into at least one secure address region, in accordance with a determination that the startup state satisfies an operating state condition. Example implementations also include a method of generating a secure partition associated with a non-transitory memory device by identifying a target processing instruction restricted to execution at a secure subsystem of a processing device, assigning to the target processing instruction a secure address, associating the secure address with a secure address region of a non-transitory memory device of the processing device, and generating a secure partition table including the secure address.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: January 23, 2024
    Assignee: Renesas Electronics Corporation
    Inventors: David Noverraz, Paul Bell, Kennedy Ho
  • Patent number: 11881806
    Abstract: A resolver converter includes a tracking loop circuit that calculates an angle ? from a resolver output signal, a control and diagnosis circuit that controls the tracking loop circuit and diagnoses based on the resolver output signal, wherein the control and diagnosis circuit, by operating the tracking loop circuit as a direct digital synthesizer (DDS), synchronously detects a noise signal superimposed on the resolver output signal.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: January 23, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Umamichi
  • Publication number: 20240022211
    Abstract: A semiconductor device includes a crystal oscillator circuit, a first noise application circuit, and a second noise application circuit. The first noise application circuit is connected to the crystal oscillator circuit and is configured to drive a crystal resonator by selectively applying initial noises of opposite phases to a first external terminal and a second external terminal. The second noise application circuit applies a second noise to the first external terminal by amplifying a signal at the first external terminal and returning the amplified signal to the first external terminal, thereby driving an oscillation amplifier and a crystal resonator of the crystal oscillator circuit and shortening a start-up time of the crystal oscillator circuit.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 18, 2024
    Applicant: Renesas Electronics Corporation
    Inventor: Soshiro NISHIOKA
  • Patent number: 11876879
    Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: January 16, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Christian Mardmoeller, Dnyaneshwar Kulkarni, Thorsten Hoffleit
  • Patent number: 11876127
    Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: January 16, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomohiro Imai, Yoshito Nakazawa, Katsumi Eikyu
  • Patent number: 11868277
    Abstract: The data processing apparatus includes a memory protection setting storage unit capable of storing a plurality of address sections as memory protection setting targets, a plurality of first determination units provided for each of the address sections stored in the memory protection setting storage unit and provisionally determining whether or not an access request is permitted based on whether or not an access destination address specified by the access request corresponds to the address section acquired from the memory protection setting storage unit, and a second determination unit finally determining whether or not the access request is permitted based on the classification information and the results of provisional determinations by the first determination unit.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: January 9, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuhiro Sugita
  • Patent number: 11868654
    Abstract: A semiconductor device includes: a nonvolatile memory cell including first memory cells and second memory cells; a bit latch; and a saved register. In a first writing operation, first writing data are stored in the bit latch and the saved register, and writing to the first memory cells is executed based on the first writing data. During the first writing operation, the first writing operation is interrupted based on a suspension command, and a second writing operation is executed. In the second writing operation, second writing data are stored in the bit latch, and writing to the second memory cells is executed based on the second writing data. After the second writing operation is ended, the first writing data is reset to the bit latch based on a resume command, and the interrupted first writing operation is restarted based on the first writing data reset to the bit latch.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 9, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takanori Moriyasu, Kazuo Yoshihara, Takayuki Nishiyama
  • Patent number: 11860225
    Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: January 2, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Fukumi Unokuchi, Toshitsugu Ishii
  • Publication number: 20230412169
    Abstract: A first P-type transistor and a second P-type transistor are connected in series between a power supply terminal and an output terminal. A first N-type transistor and a second N-type transistor are connected between a ground terminal and a power supply terminal. The second N-type transistor and the second P-type transistor are complementarily turned on and off in accordance with an input signal. A gate voltage control circuit changes at least one of the gate voltage of the P-type transistor whose drain is electrically connected to the output terminal and the gate voltage of the N-type transistor by following the output voltage VOUT of the output terminal while keeping the P-type transistor or the N-type transistor on-states.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 21, 2023
    Applicant: Renesas Electronics Corporation
    Inventor: Koji TAKAYANAGI
  • Patent number: 11847078
    Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: December 19, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki
  • Patent number: 11845387
    Abstract: A semiconductor device includes an operation resource which performs a plurality of ECU functions, a peripheral resource which is shared by the plurality of ECU functions and a control mechanism which controls a period in which one of the ECU functions uses the peripheral resource. The control mechanism calculates, based on a budget value which is given in advance and is a performance allocation, a use prohibition period in which the one of the ECU functions is prohibited from using the peripheral resource within the predetermined unit time.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: December 19, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masayuki Daito
  • Patent number: 11843371
    Abstract: A semiconductor device of the present invention includes: a P-type output transistor configured to have a source to which a power supply voltage is applied, and a drain connected to an external connection pad; a gate wiring configured to be connected to a gate of the output transistor; a signal transmitting portion configured to transmit an input signal to the gate wiring; and a voltage-breakdown protecting portion configured to apply the power supply voltage to a back gate of the output transistor if a voltage on the external connection pad is equal to or lower than the power supply voltage, or the voltage-breakdown protecting portion bringing the signal transmitting portion into a disconnection state and applies the voltage on the external connection pad to the gate and the back gate of the output transistor if the voltage applied on the external connection pad is higher than the power supply voltage.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: December 12, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Fumiaki Yanagihashi
  • Patent number: 11838393
    Abstract: A message handler is described. The message handler is configured, in response to receiving a data package which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package-directing data and payload data, to generate package having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header and payload data. The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package having a predetermined data format may be an IEEE 1722 frame.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: December 5, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Christian Mardmoeller, Dnyaneshwar Kulkarni, Thorsten Hoffleit
  • Publication number: 20230387924
    Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.
    Type: Application
    Filed: April 26, 2023
    Publication date: November 30, 2023
    Applicant: Renesas Electronics Corporation
    Inventors: Yusuke IMANAKA, Atsushi MOTOZAWA
  • Patent number: 11830944
    Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 28, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Koshimizu, Yasutaka Nakashiba
  • Patent number: 11830939
    Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: November 28, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomohiro Imai, Yoshito Nakazawa, Katsumi Eikyu