Patents Assigned to Renesas Technology
-
Publication number: 20100171183Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.Type: ApplicationFiled: March 19, 2010Publication date: July 8, 2010Applicant: Renesas Technology Corp.Inventors: Tadashi YAMAGUCHI, Keiichiro Kashihara, Tomonori Okudaira, Toshiaki Tsutsumi
-
Patent number: 7752526Abstract: The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable.Type: GrantFiled: May 14, 2007Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
-
Patent number: 7750464Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.Type: GrantFiled: January 25, 2008Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
-
Patent number: 7750668Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Type: GrantFiled: October 31, 2007Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Masashi Horiguchi, Kunio Uchiyama, Kiyoo Itoh, Takeshi Sakata, Masakazu Aoki, Takayuki Kawahara
-
Patent number: 7750463Abstract: A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.Type: GrantFiled: December 28, 2007Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Michitaka Osawa, Takamitsu Kanazawa
-
Patent number: 7752527Abstract: A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.Type: GrantFiled: November 28, 2006Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Hiromichi Yamada, Teppei Hirotsu, Teruaki Sakata, Takeshi Kataoka, Shunichi Iwata
-
Patent number: 7750427Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.Type: GrantFiled: January 6, 2009Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
-
Patent number: 7750586Abstract: A drive control device of motor capable of starting up even a motor of such a type that the polarity of induced voltage does not switch every 180° of electrical angle or the polarity, positive or negative, does not occur with accuracy without causing a reverse rotation is provided. In a start-up control of motor, the following operation is performed: a current is passed through any coils in two phases, and the polarity of voltage induced in the non-conducting phase is detected. A conducting phase at start-up is determined based on the detected polarity of induced voltage. The average value of induced voltages in non-conducting phase detected with respect to the coils in respective phases is determined. The average value and the detected induced voltages are compared with each other, and relative polarities are determined from the magnitude relation with the average value to determine a conducting phase at start-up.Type: GrantFiled: August 4, 2008Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Minoru Kurosawa, Yasuhiko Kokami
-
Patent number: 7751255Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: GrantFiled: September 19, 2008Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
-
Publication number: 20100167468Abstract: A method of manufacturing a semiconductor device includes a bonding step of bonding a chip on a wiring board by means of a bonding layer, and a wire bonding step of bonding a wire to a pad on the chip while applying ultrasonic vibration after the bonding step. A material having an elastic modulus of 100 MPa or higher at a process temperature in the wire bonding step is used as the bonding layer.Type: ApplicationFiled: December 28, 2009Publication date: July 1, 2010Applicant: Renesas Technology Corp.Inventors: Hirohisa SHIMOKAWA, Naoki Izumi
-
Publication number: 20100165691Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Applicant: Renesas Technology Corp.Inventors: Naoya WATANABE, Isamu HAYASHI, Teruhiko AMANO, Fukashi MORISHITA, Kenji YOSHINAGA, Mihoko AKIYAMA, Shinya MIYAZAKI, Masakazu ISHIBASHI, Katsumi DOSAKA
-
Publication number: 20100164613Abstract: A semiconductor device includes: a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode; a second transistor having a control electrode coupled to the input node, a first conductive electrode coupled to the output node, and a second conductive electrode coupled to a power supply node; and a first switch element connected between the power supply node and the second conductive electrode of the second transistor and turned on and off based on a first control signal indicating a detection result of a frequency of the clock.Type: ApplicationFiled: March 12, 2010Publication date: July 1, 2010Applicant: Renesas Technology Corp.Inventor: Teruyuki ITO
-
Publication number: 20100167525Abstract: A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered.Type: ApplicationFiled: March 10, 2010Publication date: July 1, 2010Applicant: Renesas Technology Corp.Inventors: Noboru Morimoto, Masahiko Fujisawa, Daisuke Kodama
-
Publication number: 20100167492Abstract: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Applicant: Renesas Technology Corp.Inventor: Toshiaki IWAMATSU
-
Publication number: 20100165775Abstract: In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The fuse program circuit provided with fuse elements that can be programmed even after packaging is implemented with low power consumption and a low occupation area.Type: ApplicationFiled: March 12, 2010Publication date: July 1, 2010Applicant: Renesas Technology Corp.Inventors: Shigeki OBAYASHI, Toshiaki Yonezu, Tokeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Takahiro Uchida
-
Patent number: 7746147Abstract: A level shifter circuit of the present invention includes a level shifter for converting a low-voltage signal to a high-voltage signal, and is provided with a unit that sets a voltage condition of an input signal to a transistor for input of the level shifter, when a high-voltage power supply is inputted to the level shifter circuit of the present invention before a low-voltage power supply.Type: GrantFiled: June 26, 2008Date of Patent: June 29, 2010Assignee: Renesas Technology Corp.Inventors: Masahide Kiritani, Noriko Sonoda
-
Patent number: 7747538Abstract: A memory card 110 extracts a session key Ks from the data applied onto a data bus BS3 by carrying out a decryption process. An encryption processing unit 1406 encrypts a public encryption key KPcard(1) of memory card 110 based on session key Ks, and applies the encrypted key to a server via data bus BS3. A memory 1412 receives from a server data such as license key Kc, license ID data License-ID and user ID data User-ID encrypted with a public encryption key KPcard(1) differing for each memory card for storage, and receives encrypted content data [Dc]Kc encrypted with license key Kc from data bus BS3 for storage.Type: GrantFiled: November 1, 2005Date of Patent: June 29, 2010Assignees: Fujitsu Limited, Renesas Technology Corp., Sanyo Electric Co., Ltd.Inventors: Masayuki Hatanaka, Jun Kamada, Takahisa Hatakeyama, Takayuki Hasebe, Seigou Kotani, Shigeki Furuta, Takeaki Anazawa, Tadaaki Tonegawa, Toshiaki Hioki, Miwa Kanamori, Toshihiro Hori
-
Patent number: 7746253Abstract: The present invention is directed to reduce offset error voltage in a signal source impedance of analog input signal voltage supplied to an input terminal due to input offset voltage of an operational amplifier in a sampling circuit or a multiplexer coupled to an input terminal of an A/D converter. A semiconductor integrated circuit has an A/D converter and a sampling circuit. The sampling circuit samples an analog input signal in first and second sample modes. The A/D converter converts the sampled analog signal to a digital signal in a conversion mode. By switching of an internal circuit of an operational amplifier between the first and second sample modes, the functions of a non-inverting input terminal (+) and an inverting input terminal (?) realized by first and second input terminals are switched. Synchronously with the switching, supply of an analog signal to the non-inverting input terminal by input switches is also switched.Type: GrantFiled: November 25, 2008Date of Patent: June 29, 2010Assignee: Renesas Technology Corp.Inventors: Akira Kitagawa, Akihiro Kitagawa
-
Patent number: 7745288Abstract: A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.Type: GrantFiled: March 13, 2007Date of Patent: June 29, 2010Assignee: Renesas Technology Corp.Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Kentaro Saito, Toshikazu Matsui, Takashi Hashimoto, Kosuke Okuyama
-
Patent number: 7745915Abstract: A mounting board has a plurality of semiconductor memory devices operated in sync with a clock signal, and a semiconductor data processing device which access-controls the semiconductor memory devices. Layouts of data-system terminals of the semiconductor memory devices with respect to memory access terminals of the semiconductor data processing device are determined in such a manner that wirings for data and a data strobe system (RTdq/dqs) become shorter than wirings for a command/address system (RTcmd/add). The wirings for the data and data strobe system (RTdq/dqs) are laid down using an area defined between the semiconductor memory devices. The wirings for the command/address system (RTcmd/add) bypass the side of the mounting board.Type: GrantFiled: February 24, 2006Date of Patent: June 29, 2010Assignee: Renesas Technology Corp.Inventors: Motoo Suwa, Hikaru Ikegami, Takafumi Betsui