Patents Assigned to Renesas Technology
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Patent number: 7728421Abstract: Plural via portions formed on a package substrate of a BGA include a first through-hole portion extended in the plane direction by an extension wiring connected to a land portion and a second through-hole portion that is arranged on the land portion serving as pad-on-via, whereby high-density wiring and multi-function of the BGA can be realized by using the package substrate having a two-layer wiring structure. Accordingly, cost for the package substrate can be reduced, and hence, cost for the BGA can be reduced, compared to a multi-layer wiring structure having four or six wiring layers.Type: GrantFiled: January 24, 2007Date of Patent: June 1, 2010Assignee: Renesas Technology Corp.Inventor: Tetsuharu Tanoue
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Patent number: 7728678Abstract: A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit.Type: GrantFiled: October 17, 2008Date of Patent: June 1, 2010Assignee: Renesas Technology Corp.Inventor: Katsuyoshi Mitsui
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Patent number: 7727709Abstract: The present invention improves the OPE characteristic generated by the difference between sparse and dense mask patterns and promotes fidelity in the design of the pattern. Because of this, the present invention includes a step of forming a resist having an acid dissociative dissolution suppression group on a substrate, a step of coating the resist with an acid polymer dissolved in an alcohol based solvent and forming an upper layer film, a step of exposing through a mask, a step of performing a baking process, and a step of processing with an alkali developer, and wherein in the step of performing a baking process, a mixing layer is formed on the resist by the upper layer film and in which a thicker mixing layer is formed in an unexposed part of a region where the pattern density of the mask pattern is high compared to a region where the pattern density is low.Type: GrantFiled: January 31, 2007Date of Patent: June 1, 2010Assignee: Renesas Technology Corp.Inventors: Toshifumi Suganaga, Tetsuro Hanawa, Takeo Ishibashi
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Patent number: 7723131Abstract: Speed-up of a die bonding process for mounting a semiconductor chip onto a wiring substrate and improvement of a semiconductor package manufacturing yield are to be attained. A paste applicator comprises a drive section and a movable section supported by the drive section. The movable section includes a holder body adapted to move vertically along a main shaft with rotation of a motor in the drive section and a nozzle holder screwed to the holder body. A nozzle secured to a lower end of a syringe is screwed to the nozzle holder. Using a height sensor fixed to a main shaft support portion in the drive section, the paste applicator detects a positional deviation quantity with time of the movable section relative to the drive section and corrects a descent distance of the movable section on the basis of the positional deviation quantity.Type: GrantFiled: July 22, 2005Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventor: Shuetsu Yoshino
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Patent number: 7725665Abstract: A data processor (1) has a central processing unit (3) and a memory controller (6) capable of controlling a memory (8) to be connected to an outside. The memory has a buffer capable of temporarily holding data within an address range corresponding to a predetermined bit number on a low order side of an address signal, and a burst operation for inputting/outputting data can be carried out by a data transfer between the buffer and the outside for an access request in which an access address is changed within the address range. When causing the memory to carry out the burst operation to give an access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects an access exceeding the address range. When causing the memory to carry out the burst access, the memory controller performs an access control for freely executing the burst operation of the memory continuously if it detects the access exceeding the address range.Type: GrantFiled: June 30, 2004Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Masayoshi Horishima, Hajime Sasaki, Takashi Koshido
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Patent number: 7725124Abstract: An object of the present invention is to provide a transmitter-receiver RF-IC having a built-in regulator, which can reduce a minimum value of an input voltage of the regulator without increasing its area, the input voltage being supplied from a battery, the transmitter-receiver RF-IC being capable of normal operation with the input voltage, whereby the operating time of a mobile terminal can be improved as compared with the prior art. According to the present invention, in order to achieve the above object, an output end of a regulator built into a RF-IC is first led to the outside of the RF-IC. Then, the output end is led to an area in proximity to the circuit block by use of wiring on a mobile terminal substrate whose resistance is low, or by use of wiring on a module whose resistance is low, thereby shortening the wiring length inside the RF-IC.Type: GrantFiled: October 11, 2005Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Taizo Yamawaki, Yoshiaki Harasawa
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Patent number: 7725616Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: June 4, 2008Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Patent number: 7723779Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.Type: GrantFiled: May 22, 2006Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Digh Hisamoto, Shin'ichiro Kimura, Daiske Okada, Kan Yasui
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Patent number: 7724006Abstract: A silicon substrate is used as a mold, and thin films such as metal films and polyimide films are sequentially stacked on the silicon substrate by using photolithography techniques, thereby forming a probe sheet having contact terminals having a pyramidal shape or a truncated pyramidal shape disposed at distal ends of cantilever beam structures. A fixing substrate is further fixed to the probe sheet, and then, the formed probe sheet is sequentially stacked and formed on the silicon substrate, the substrate is fixed, and the silicon substrate and predetermined polyimide films are removed by etching, thereby forming the group of contact terminals with the cantilever beam structures at a time.Type: GrantFiled: October 17, 2008Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Susumu Kasukabe, Yasunori Narizuka
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Patent number: 7724269Abstract: A display driver used in common for a first screen and a second screen. The display driver includes a data line drive circuit which supplies gray scale voltages to the first and second screens in accordance with display data via data lines in common for the first and second screens, and a scan line drive circuit which supplies scan signals to the first and second screens via scan lines, with the scan lines in the first screen being different from the scan lines in the second screen. The scan line drive circuit scans the second screen in one of a one-line-at-a-time operation and a plural-line-at-a-time operation by using the scan signals every time the scan line drive circuit scans at least one frame of the first screen in a one-line-at-a-time operation by using the scan signals.Type: GrantFiled: January 30, 2007Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Yasuyuki Kudo, Kazuo Okado, Hiroki Aizawa
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Patent number: 7723849Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: GrantFiled: December 28, 2006Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
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Patent number: 7724265Abstract: A YUV format to be stored in a memory is selected from A or B by a format judging unit for RGB data that is the input output display data of a memory unit, based on the comparison between chrominance (U, V) difference information on horizontal two pixels and the threshold values of U difference and V difference to be resistor-set at a format judging unit. The YUV data and information of A or B that are YUV format-converted at the format conversion unit are stored in the memory. The selection of the YUV format of A or B is, when the chrominance difference information is small as compared with the threshold value the format is YUV 422 (B conversion), and when it is large the format is that the low order bits of Y, U, V of each pixel are reduced (A conversion).Type: GrantFiled: October 11, 2006Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Naoki Takada, Yasuyuki Kudo, Goro Sakamaki
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Patent number: 7724606Abstract: A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.Type: GrantFiled: July 30, 2007Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Tokuya Osawa, Masaru Haraguchi, Yoshikazu Morooka, Hiroshi Kinoshita
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Patent number: 7722962Abstract: A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side in temperature-hierarchical bonding, and semiconductor devices and electronic devices produced by use of such solder bonding have distinguished reliability of mechanical characteristics, etc.Type: GrantFiled: December 19, 2001Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Tasao Soga, Hanae Hata, Toshiharu Ishida, Kanko Ishida, legal representative, Tetsuya Nakatsuka, Masahide Okamoto, Kazuma Miura
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Patent number: 7723790Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.Type: GrantFiled: September 11, 2008Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
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Patent number: 7722437Abstract: A polishing pad used in a CMP step in the manufacture of a semiconductor integrated circuit device is relatively expensive; thus, it is necessary to avoid a wasteful exchange of the pad. Accordingly, it is important to measure the abrasion amount of this pad precisely. However, in ordinary measurement thereof through light, the presence of a slurry hinders the measurement. In measurement thereof with a contact type sensor, a problem that pollutants elute out is caused. In a CMP step in the invention, the height position of a dresser is measured while the dresser operates, thereby detecting the abrasion amount or the thickness of a polishing pad indirectly. In this way, the time for exchanging the polishing pad is made appropriate.Type: GrantFiled: May 8, 2008Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventor: Yoshinori Ito
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Patent number: 7723753Abstract: In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.Type: GrantFiled: December 21, 2007Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Kenji Sasaki, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
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Patent number: 7723235Abstract: After a polycrystalline silicon film (5) is formed on a semiconductor substrate via an insulating film for a gate insulating film (step S1), an organic antireflection film (21) is formed on the polycrystalline silicon film (5) (step S2), and a resist pattern (22) is formed on the antireflection film (21) (step S3). Then, a passivation film (23) is deposited on the antireflection film (21) so as to cover the resist pattern (22) by plasma using fluorocarbon gas while a bias voltage is being applied to the semiconductor substrate (step S4). Then, the passivation film (23) and the antireflection film (21) are etched by plasma using gas containing oxygen gas (step S5). Thereafter, the polycrystalline silicon film (5) is etched using the resist pattern (22) with reduced line edge roughness as an etching mask to form a gate electrode (step S6).Type: GrantFiled: June 10, 2005Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Masaru Kurihara, Masaru Izawa
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Patent number: 7723937Abstract: A motor drive control device and motor startup method prevent startup noise and reduce startup time. At startup, a current to which a rotor does not react is passed through two phase coils of a polyphase DC motor in succession, and a voltage polarity induced in a non-conducting phase is detected. A first operation decodes the detected signal, and determines phase coils of the motor through which a current should pass to rotate the rotor and the energization direction. A second operation forms a control signal for passing a current according to the determination to drive the motor, detects a voltage peak induced in the non-conducting phase during the drive, and performs switching control of a conducting phase. In normal operation, the position of the rotor is detected based on a back EMF in each phase, and rotation control is performed.Type: GrantFiled: October 12, 2007Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Minoru Kurosawa, Yasuhiko Kokami
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Patent number: 7725847Abstract: A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer.Type: GrantFiled: November 1, 2004Date of Patent: May 25, 2010Assignees: Mitsubishi Denki Kabushiki Kaisha, Renesas Technology Corp.Inventors: Akihiro Goto, Hironori Matsushima, Hiroshige Ogawa, Yoshio Matsuda