Patents Assigned to Renesas Technology
  • Patent number: 7767522
    Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: August 3, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Takashi Hashimoto
  • Patent number: 7768294
    Abstract: The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: August 3, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhisa Shimazaki, Masakazu Nishibori
  • Patent number: 7769980
    Abstract: In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: August 3, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Toshinori Sueyoshi, Masahiro Iida, Mitsutaka Nakano, Fumiaki Senoue, Katsuya Mizumoto
  • Publication number: 20100190330
    Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.
    Type: Application
    Filed: March 19, 2010
    Publication date: July 29, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Yasuaki YONEMOCHI, Hisakazu Otoi, Akio Nishida, Shigeru Shiratake
  • Publication number: 20100190306
    Abstract: A method of manufacturing a semiconductor device is provided that can suppress impurity concentration reduction in a doped channel region arising from formation of a gate insulating film. With a silicon oxide film and a silicon nitride film being formed, p-type impurity ions are implanted in a Y direction from diagonally above. As for an implant angle ? of the ion implantation, an implant angle is adopted that satisfies the relationship tan?1 (W2/T)<??tan?1 (W1/T), where W1 is an interval between a first portion and a fourth portion and an interval between a third portion and a sixth portion; W2 is an interval between a second portion and a fifth portion; T is a total film thickness of the silicon oxide film and the silicon nitride film. When the implant angle ? is controlled within that range, impurity ions are implanted into a second side surface and a fifth side surface through a silicon oxide film.
    Type: Application
    Filed: April 5, 2010
    Publication date: July 29, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Yoshinori Tanaka, Katsuyuki Horita, Heiji Kobayashi
  • Publication number: 20100191883
    Abstract: An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.
    Type: Application
    Filed: March 12, 2010
    Publication date: July 29, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Hideo Nagano, Kikuo Muramatsu, Masayuki Koyama, Tomoko Ando, Motoki Higashida, Takahiko Arakawa, Makoto Hatakenaka
  • Publication number: 20100187678
    Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 29, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Ryoichi KAJIWARA, Shigehisa MOTOWAKI, Kazutoshi ITO, Toshiaki ISHII, Katsuo ARAI, Takuya NAKAJO, Hidemasa KAGII
  • Patent number: 7763926
    Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Masahiko Takeuchi
  • Patent number: 7765415
    Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hiromichi Ishikura, Toyohiro Shimogawa, Katsumasa Uchiyama, Shoichiro Chiba, Naoki Handa
  • Patent number: 7765269
    Abstract: This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corporation
    Inventors: Nobuyasu Kanekawa, Hiromichi Yamada, Kohei Sakurai, Kotaro Shimamura, Yuichiro Morita, Satoshi Tanaka
  • Patent number: 7763967
    Abstract: A semiconductor device has a sealing body formed of an insulating resin and a semiconductor chip positioned within the sealing body. A gate electrode and a source electrode are on a first main surface of the semiconductor chip and a back electrode (drain electrode) is on a second main surface thereof. An upper surface of a portion of a drain electrode plate that projects in a gull wing shape is exposed from the sealing body and a lower surface thereof is connected to the back electrode through an adhesive. A gate electrode plate projects in a gull wing shape on an opposite end side of the sealing body and is connected to the gate electrode within the sealing body. A source electrode plate projects in a gull wing shape on the opposite end side of the sealing body and is connected to the source electrode within the sealing body.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Toshiyuki Hata, Takeshi Otani, Ichio Shimizu
  • Patent number: 7764536
    Abstract: A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disables at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: July 27, 2010
    Assignees: Grandis, Inc., Renesas Technology Corp.
    Inventors: Xiao Luo, David Chang-Cheng Yu
  • Patent number: 7764540
    Abstract: By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Fukashi Morishita, Kazutami Arimoto
  • Patent number: 7764209
    Abstract: A CPU outputs digital data from a built-in RAM to a buffer in response to a request from the buffer. The buffer has a FIFO configured of a plurality of stages, each stage of the FIFO is capable of storing one unit (10 bits) of digital data, the buffer as a whole is capable of storing digital data in number of units equivalent to the number of configured stages. A register captures digital data stored inside the buffer by each unit in synchronous with an output control clock. The digital data stored in the register is outputted to a parallel DAC as data for D/A conversion. A WR signal output timer generates a writing control signal having one shot pulse of ā€œLā€ in synchronous with the output control clock.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Isao Tottori, Masaru Hagiwara
  • Patent number: 7763966
    Abstract: A plurality of inner leads 14 are provided around a die pad 13. A grounded GND lead 16 is provided in a region between the die pad 13 and the plurality of inner leads 14. A semiconductor chip 17 and the plurality of inner leads 14 are connected to each other by a plurality of wires 21. The semiconductor chip 17 and the GND lead 16 are connected to each other by GND wires 22. The GND wires 22 are disposed between a plurality of wires 21. The distance between ends of each adjacent pair of the inner leads 14 is 0.2 mm or less.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyuki Misumi, Kazushi Hatauchi, Yasuki Takata, Naoya Yasuda, Hideyuki Arakawa, Katsuyuki Fukudome
  • Patent number: 7764731
    Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hideki Uchiki, Atsuhiko Ishibashi
  • Patent number: 7765250
    Abstract: There is provided at least one processor block including a plurality of load store interfaces (801, 804), a plurality of memory banks (821), an input/output port having at least one of an input port (850) and an output port (860), and a crossbar switch (810), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: July 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takanobu Tsunoda, Bryan Atwood, Masashi Takada, Hiroshi Tanaka
  • Publication number: 20100181628
    Abstract: Prevention of disconnection of a bonding wire resulting from adhesive interface delamination between a resin and a leadframe, and improvement of joint strength of the resin and the leadframe are achieved in a device manufactured by a low-cost and simple processing. A boss is provided on a source lead by a stamping processing, and a support pillar is provided in a concave portion on a rear side of the source lead in order to prevent ultrasonic damping upon joining the bonding wire onto the boss, so that an insufficiency of the joint strength between the bonding wire and the source lead is prevented. Also, a continuous bump is provided on the boss so as to surround a joint portion between the source lead and the bonding wire, so that disconnection of the bonding wire resulting from delamination between the resin and the source lead is prevented.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 22, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Kenya Kawano, Kisho Ashida, Kuniharu Muto, Ichio Shimizu, Tomibumi Inoue
  • Patent number: 7759743
    Abstract: A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a P well voltage is provided in a third metal interconnection layer. The metal supplying the N well voltage is formed using a metal in the first metal interconnection layer and thus does not require a piling region to the underlayer, and only a piling region to the underlayer of the metal for the P well voltage needs to be secured. Therefore, the length in the Y direction of a power feed cell can be reduced thereby reducing the layout area of the power feed cell.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Yuichiro Ishii
  • Patent number: 7759763
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka