Abstract: In this REID card issuing system, manual operations are required only in two steps of: inputting personal information of an RFID card holder to register it in database; and pushing a shutter button of a camera when a photograph is being taken. Also, software controls are employed for the steps of: copying an image file of a computer COM4 from the camera CAM, changing the file name to a suitable name, and registering the name in the database to associate it with the personal information; printing the image file and personal information on a new card NC; and reading an ID number from an inlet stuck to a rear surface of the new card NC during the printing and registering the ID number in the database to associate it with the personal information and image file. Therefore, it is possible to reduce the issuing time and simplify the issuing process of the RFID card.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.

Abstract: A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.

Abstract: As external connection terminals for an emitter electrode (12) of an IGBT chip, a first emitter terminal (151) for electrically connecting a light emitter in a strobe light control circuit to the emitter electrode (12) and a second emitter terminal (152) for connecting a drive circuit for driving an IGBT device to the emitter electrode (12) are provided. The first emitter terminal (151) and the second emitter terminal (152) are individually connected to the emitter terminal (12) by wire bonding.

Abstract: In a switching power supply apparatus for performing a switching control of a power MOS transistor that flows current to a coil and converting input voltage into output voltage, even if there occurs offset voltage in a current sensing operational amplifier, source potential of a current sensing MOS transistor is precisely kept at source potential of a low side power MOS transistor. For example, an offset cancel capacitor is arranged at an inverting input terminal of the current sensing operational amplifier, and voltage in the direction to offset the offset voltage occurring in the operational amplifier is charged to this capacitor.

Abstract: A cleaning sheet (29) is formed with a trough-hole (29a) at a portion corresponding to a cavity of a mold along with a slit (29b) or a flow cavity cut (29c) at every corner at an outer periphery of the through-hole (29a) and is placed between a first mold half and a second mold half of the mold to clean the inside of the mold, thereby improving the cleaning effect of the mold.

Abstract: A demodulating semiconductor integrated circuit device used in a wireless communication system of an FM-modulation scheme, wherein a circuit for canceling a frequency offset is made of a digital circuit, so as to make a high-accuracy decision as to received data and prevent error frequency offset cancel due to a pseudo pattern contained in the received data. Consequently, a high-accuracy received data decision is carried out.

Abstract: A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.

Abstract: A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant (29), a plurality of outer leads (37), (38) protruding in parallel from the same lateral surface of the resin encapsulant (29) and a header (28) bonded to a back surface of the semiconductor pellet and having a header protruding portion (28c) protruding from a lateral surface of the resin encapsulant (29) opposite to the lateral surface from which the outer leads protrude, wherein the header (28) has an exposed surface (28b) exposed from the resin encapsulant (29); the outer leads (37), (38) are bent; and the exposed of the outer leads (37), (38) are provided at substantially the same height.

Abstract: In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C1, C2) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract: A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.

Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.

Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.

Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

Abstract: A frequency mixer includes a first N channel MOS transistor, second and third N channel MOS transistors constituting a local oscillator signal differential pair, and having substantially identical properties, a first load, and a second load. The first N channel MOS transistor receives an RF signal at its gate. A local oscillator signal is applied to the gates of the second and third N channel MOS transistors. The drain current of the second and third N channel MOS transistors is output to the drain of the first N channel MOS transistor. An amplitude-current conversion circuit receives the RF signal and provides an output current to the drain of the first N channel MOS transistor to decrease monotonously the output current with respect to the amplitude of the RF signal.

Abstract: In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.

Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.

Abstract: A semiconductor device includes: a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down; and an internal voltage determining circuit for determining voltage of the internal power supply in which power is shut down. Voltage of the internal power supply in which power is shut down is generated from external power supply voltage by using a regulator circuit. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, increased voltage of the internal power supply is determined, operation of a circuit block is started, and the switch is turned on.