Patents Assigned to Renesas Technology
  • Patent number: 7371606
    Abstract: The yield of a sealing process for a semiconductor device which adopts a flip-chip mounting method is to be improved. In a molding process wherein plural semiconductor chip ICs mounted on a parts mounting surface of a substrate matrix through bump electrodes are to be sealed all together with a sealing resin in a reduced state of the internal pressure of a cavity of a molding apparatus, a clamping pressure at the time of clamping the substrate matrix by both a lower die and an upper die of a molding die is set at a relatively low pressure in an initial stage of injection of the sealing resin and is changed to a relatively high pressure when the sealing resin has covered the semiconductor chip ICs located in a final stage in the resin injecting direction.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Ujiie, Bunji Kuratomi
  • Patent number: 7371631
    Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
  • Patent number: 7371681
    Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Kazuyoshi Maekawa
  • Patent number: 7372882
    Abstract: A driving circuit supplies a suppression current (I4) which reduces a decrease in a driving current (Idrive) immediately after occurrence of an overshoot at the time of the rise of the driving current (Idrive) to a laser diode (1). The driving circuit draws a suppression current (I5) which reduces an increase in the driving current (Idrive) immediately after occurrence of an undershoot at the time of the fall of the driving current (Idrive) from the driving current (Idrive).
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tsuyoshi Horiuchi, Takehiko Umeyama
  • Patent number: 7372245
    Abstract: A difference between both emitter voltages of a first transistor having an emitter through which a first current flows, and at least one second transistor having an emitter through which such a second current as to reach a current density thereof smaller than that of the emitter of the first transistor flows, is applied across a first resistor. A second resistor is provided between the emitter of the second transistor and a circuit's ground potential. A third resistor and a fourth resistor are respectively provided between collectors of the first and second transistors and a power supply voltage. Such an output voltage that a collector voltage of the first transistor and a collector voltage of the second transistor become equal is formed in response to the collector voltage of the first transistor and the collector voltage of the second transistor and supplied to bases of the first and second transistors in common.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Masashi Horiguchi, Tadashi Kameyama
  • Patent number: 7368776
    Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: May 6, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Tanaka, Masahiro Shimizu, Hideaki Arima
  • Patent number: 7369429
    Abstract: A tunneling magneto-resistance element is arranged on an upper layer side of a digit line. The tunneling magneto-resistance element is electrically coupled to a source/drain region of an access transistor through a strap and a contact hole. A bit line is electrically coupled to the tunneling magneto-resistance element, and arranged on the upper layer side of the tunneling magneto-resistance element. A plurality of tunneling magneto-resistance elements share one access transistor, so that a non-volatile memory device achieving low area penalty and higher integration can be implemented.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: May 6, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Hiroaki Tanizaki
  • Patent number: 7370131
    Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: May 6, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hideo Inoue, Isao Minematsu, Takahiro Ikenobe
  • Patent number: 7368988
    Abstract: In a base-bias-control-type high-frequency power amplifier with a plural stage configuration, a rising voltage of a base bias current supplied to an initial stage transistor is made lower than a rising voltage of a base bias current supplied to a second stage transistor by a bias circuit, and a difference between the both voltages is set to be smaller than a base-emitter voltage of an amplifying stage transistor. Also, a rising voltage of a base bias current supplied to a third stage transistor is made equal to the rising voltage of the base bias current supplied to an initial stage transistor. Accordingly, a technology capable of improving the power control linearity can be provided in a high-frequency power amplifier used in a polar-loop transmitter or the like.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: May 6, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hidetoshi Matsumoto, Tomonori Tanoue, Isao Ohbu
  • Patent number: 7369817
    Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: May 6, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kumiko Takikawa, Satoshi Tanaka, Takashi Hashimoto, Yoshiyuki Okabe
  • Patent number: 7368996
    Abstract: Disclosed is a power amplifier having highly stable and excellent controllability, and having low noise in comparison with conventional power amplifiers. With the power amplifier, a differential amplifier made up of transistors Q1, Q2 is provided in the initial stage thereof, and baluns doubling as inter-stage matching circuits, comprised of Cp1, Cp2, Lp1, and Ct1, Ct2, Lt1, respectively, are provided between the initial stage, and a second stage while an unbalanced single-ended circuit is provided in the second stage. The differential amplifier has an emitter-coupled type configuration for coupling both emitters with each other, and output control of the amplifier in the initial stage is executed by varying current of a current source coupled to both the emitters.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: May 6, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tomonori Tanoue, Masami Ohnishi, Hidetoshi Matsumoto, Akira Kuriyama
  • Patent number: 7370168
    Abstract: The invention intends to provide a memory card conforming to an HS-MMC mode in a standard of a multimedia card, while securing compatibility of both standards of the multimedia card and an SD card. In a normal MMC mode, the data is outputted at a fall edge of a clock signal. A frequency of the clock signal is about 20 MHz. When the data is outputted at the fall edge of the clock signal, data output is in time for a next clock signal. When a parameter ‘1’ is set to a timing register provided in a host interface, the memory card is transitioned into the HS-MMC mode. In the HS-MMC mode, a clock signal frequency is increased to about 52 MHz. Here, the data is outputted at the rise edge of the clock signal, whereby the data output is brought in time for the rise edge of the next clock signal.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: May 6, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Motoki Kanamori, Kunihiro Katayama, Yasuhiro Nakamura, Satoshi Yoshida, Shinsuke Asari
  • Publication number: 20080099813
    Abstract: A semiconductor device including a semiconductor substrate having a logic formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in said logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a capacitor formed above the first silicide film and electrically connected to the first silicide film; and a second silicide film formed in an upper surface of the fourth impurity region and having a larger t
    Type: Application
    Filed: December 11, 2007
    Publication date: May 1, 2008
    Applicant: Renesas Technology Corp.
    Inventor: Hiroki Shinkawata
  • Publication number: 20080099810
    Abstract: A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.
    Type: Application
    Filed: December 11, 2007
    Publication date: May 1, 2008
    Applicant: Renesas Technology Corp.
    Inventor: Hiroki Shinkawata
  • Patent number: 7366481
    Abstract: A polar loop based radio telecommunication apparatus which has a phase control loop for controlling the phase of a carrier outputted from an oscillator for transmitter, and an amplitude control loop for controlling the amplitude of a transmission output signal outputted from a power amplifier circuit, wherein precharge means is provided on a forward path from a current source, through the power amplifier circuit, to a detection circuit, forming the amplitude control loop, for rapidly increasing a control voltage for the power amplifier circuit to a power threshold upon starting transmission.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: April 29, 2008
    Assignees: Renesas Technology Corporation, Tipcom Limited
    Inventors: Kazuhisa Okada, Kazuhiko Hikasa, Patrick Wurm
  • Patent number: 7365426
    Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: April 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
  • Patent number: 7365433
    Abstract: The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for transmitting a signal are continuously covered by a conductor layer (12) with insulators (7), (8) and (9) interposed therebetween in a section crossing a direction of extension thereof, and the conductor layer (12) is connected to a semiconductor substrate (1). Moreover, a periphery of a wiring (15) for transmitting a signal is continuously covered by the conductor layer (12) and a conductor layer (19) with insulators (14), (16), (17) and (18) interposed therebetween in a section crossing a direction of extension thereof. The wiring (15) is electrically connected to the semiconductor substrate (1) through a conductive plug (13) filled in a contact hole (24) formed in the conductor layer (12).
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: April 29, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Masato Fujinaga
  • Patent number: 7366034
    Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: April 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
  • Patent number: 7366965
    Abstract: Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in the updating of X addresses, Y addresses, and bank addresses. A variety of addressing modes provided expand BIST-based test functions.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: April 29, 2008
    Assignee: Renesas Technology, Corp.
    Inventors: Kaname Yamasaki, Yoshio Takamine
  • Patent number: 7366489
    Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: April 29, 2008
    Assignees: TTPCOM Limited, Renesas Technology Corp.
    Inventors: Satoshi Tanaka, Kazuo Watanabe, Masao Hotta, Toyohiko Hongo, Taizo Yamawaki, Masumi Kasahara, Kumiko Takikawa