Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

Abstract: A phase shift mask includes a quartz substrate having a main surface partially dug, and a Cr film deposited on the main surface. The dug portion includes an undercut provided such that the Cr film partially serves as an eaves, and the Cr film has a ? opening exposing a portion of the dug portion, and a first subopening exposing an end of the dug portion.

Abstract: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across PN film. Polysilicon layer is patterned with second insulating film, and first gate electrode extends from PMOS region surface to PN and second gate electrode extends from NMOS region to PN connecting to first gate electrode. At main surface, opposed first source and drain regions are formed by placing first gate electrode therebetween in plan view. At main surface, opposed second source and drain regions are formed by placing second gate electrode therebetween in plan view. The second insulating film, covering first and second gate electrodes is patterned and exposed on PN. Exposed first and second gate electrodes are silicidized.

Abstract: A resist film is applied to an entire surface and subjected to patterning substantially in the same form as an opening to bury the resist film inside the opening. When a positive resist is used, a photomask having a light-shielding portion with an area smaller than the opening is used in patterning. When a negative resist is used, a photomask having a light transmitting portion with an area smaller than the opening is used.

Abstract: Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon surface, in gate electrode region extending from PMOS to NMOS regions across PN film. Polysilicon layer is patterned with second insulating film, and first gate electrode extends from PMOS region surface to PN and second gate electrode extends from NMOS region to PN connecting to first gate electrode. At main surface, opposed first source and drain regions are formed by placing first gate electrode therebetween in plan view. At main surface, opposed second source and drain regions are formed by placing second gate electrode therebetween in plan view. The second insulating film, covering first and second gate electrodes is patterned and exposed on PN. Exposed first and second gate electrodes are silicidized.

Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

Abstract: In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.

Abstract: An electrode on a semiconductor substrate includes a polysilicon layer, a silicon-implanted layer on the polysilicon layer, a tungsten nitride layer on the silicon-implanted layer, a tungsten nitride layer on the silicon-implanted layer, and a tungsten layer on the tungsten nitride layer. The layer between the polysilicon layer and the tungsten nitride layer may be either a tungsten silicon nitride layer or a silicon-germanium layer.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: When a line number counted by a line number counting unit corresponds to a prescribed line number, a transfer source address generating unit adds an offset address set in an offset address setting unit to respective transfer source addresses to output as addresses to a memory. A DMA control unit controls DMA transfer in accordance with a transfer source address generated by the transfer source address generating unit and a transfer destination address generated by a transfer destination address generating unit. Thus, rapid enlargement/reduction of image data becomes possible.

Abstract: A current source block and a negative resistance generation block are connected in parallel. The negative resistance generation block generates a negative resistance in response to the minute variations of an output voltage. Thus the output resistance of a current source circuit is given by the combined resistance of the negative resistance and the resistance of a resistor in the current source block connected in parallel. The resistance of the resistor in the current source block and the negative resistance are controlled to be substantially the same to thereby increase the output resistance of the current source circuit. The current source circuit serves to increase an output resistance when viewed from an differential output terminal. As a result, use of this current source circuit realizes a differential amplifier providing a high gain.

Abstract: An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole vertically penetrating the interlayer insulating film for exposing a surface of the etching stopper film is formed under a first etching condition. Thereafter, the etching stopper film serving as a bottom surface of the hole is removed under a second etching condition, thereby forming the hole reaching the conductive layer. An interconnection is embedded in the hole. A semiconductor device in which a hole reaching the conductive layer is prevented from extending as far as the lower interlayer insulating film as a result of misalignment, as well as a manufacturing method thereof are thus obtained.

Abstract: An imaging control unit specifies a scan region, including an effective pixel region and a blanking region, of an image based on a magnification for electronic zooming, and converts an input optical signal into an electrical signal by scanning the scan region. The imaging control unit reads the electrical signal stored and delivers the electrical signal to an image sensor unit as picture data. An RW control unit stores the picture data in a register based on the magnification for electronic zooming, and then reads the picture data at a predetermined frame rate. A resolution converter performs interpolation processing of the picture data based on the magnification for electronic zooming.

Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.

Abstract: An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.

Abstract: A semiconductor device includes a fuse wire, a portion to be fused that overlies the fuse wire with an insulation film interposed therebetween, and a plug connecting the portion to be fused and the fuse wire together. The portion to be fused underlies an insulation film having a thickness, and the fuse wire underlies an insulation film having a thickness larger than that of the insulation film overlying the portion to be fused. The insulation film overlying the fuse wire has a thickness sufficient to prevent a laser beam from blowing the fuse wire.

Abstract: In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.

Abstract: A semiconductor device mounted on a mother board has a circuit board to be positioned on the mother board and a semiconductor chip positioned on the circuit board. The circuit board has a connection pad, a relay pad spaced away from the connection pad, and a wire connecting between the connection pad and the relay pad on a surface of the circuit board supporting the semiconductor chip. Also, the semiconductor chip has a connection pad corresponding to the connection pad formed on the circuit board. Further, the connection pad on the circuit board and the connection pad on the semiconductor chip are electrically connected to each other through a bonding wire.