Abstract: A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.

Abstract: An integrated circuit chip module includes a first integrated circuit chip including a first power source pad for a first power voltage and an adjacent second power source pad for a second power voltage, the first power voltage being higher than the second power voltage, a second integrated circuit chip including a third power source pad for the first power voltage and an adjacent fourth power source pad for the second power voltage, and a wiring board including a first power source wire electrically connected to the first power source pad, a second power source wire electrically connected to the second power source pad, a third power source wire electrically connected to the third power source pad, and a fourth power source wire electrically connected to the fourth power source pad.

Abstract: A transistor is arranged for electrically isolating a sense amplifier formed of a thin film transistor from a data line electrically coupled to the sense amplifier. When a write driver drives the data line, a control signal is applied to isolate the data line from the sense amplifier.

Abstract: In the formation of a halftone type phase shift mask, a reactive gas introduction inlet and an inert gas introduction inlet are provided so as to introduce the respective gases separately and by using a reactive low throw sputtering method a molybdenum silicide based phase shifter film is formed. Thereby, it becomes possible to provide a halftone type phase shift mask, which is applicable to an ArF laser or to a KrF laser, by using molybdenum silicide based materials.

Abstract: First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.

Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.

Abstract: A semiconductor device includes a gate electrode disposed on a semiconductor layer via a gate insulating film; a source layer formed in the semiconductor layer to be separated by a first offset length from one end of said gate electrode; a drain layer formed in the semiconductor layer to be separated by a second offset length from the other end of said gate electrode; a first side wall formed at a side wall of said gate electrode at a side of said source layer; and a second side wall formed at the side wall of said gate electrode at a side of said drain layer, wherein the first offset length is shorter than the second offset length, and a length of said first side wall is shorter than a length of said second side wall.

Abstract: The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring (6) for transmitting a signal are continuously covered by a conductor layer (12) with insulators (7), (8) and (9) interposed therebetween in a section crossing a direction of extension thereof, and the conductor layer (12) is connected to a semiconductor substrate (1). Moreover, a periphery of a wiring (15) for transmitting a signal is continuously covered by the conductor layer (12) and a conductor layer (19) with insulators (14), (16), (17) and (18) interposed therebeween in a section crossing a direction of extension thereof. The wiring (15) is electrically connected to the semiconductor substrate (1) through a conductive plug (13) filled in a contact hole (24) formed in the conductor layer (12).

Abstract: First, an first insulating film is formed along surfaces of a plurality of combinations of an gate electrode and an gate insulating films, and a semiconductor substrate, respectively. Then, on the first insulating film, an second insulating film different from the first insulating film is formed. The steps of forming the first insulating film and forming the second insulating film are alternately repeated until a concave formed by the surface of an later insulating film, which is a film formed later out of the first insulating film and the second insulating film, is positioned above the upper surface of the gate electrode. Thereafter, a third insulating film is formed on the later insulating film. Thus, a semiconductor device with high reliability can be obtained by improving a state of the insulating film formed between the gate electrodes.

Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.

Abstract: A terminal resistor is provided at the end of a bus formed on a wiring substrate. An insulator having a large dielectric loss angle is provided in the vicinity of the terminal resistor to absorb high frequency electromagnetic waves in the vicinity. This arrangement permits successful transmission of digital signals in the GHz region using a conventional terminal resistor.

Abstract: An object of this invention is to prevent the NBTI degradation which may occur following the recent progress in miniaturization of the semiconductor device. By using a silicon nitride film, in which a concentration of Si—H bonds is not greater than 1×1021 cm?3, at least for a liner film or a second sidewall insulating film, the NBTI lifetime of the p-type MOS FET can be improved to be 1×109 seconds, which secures sufficient lifetime for the semiconductor integrated circuit device.

Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

Abstract: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.

Abstract: Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Abstract: The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a data read current flowing through each bit line corresponding to each memory cell of a memory cell row storing the storage information with a data read current flowing through each bit line corresponding to each retrieval memory cell storing the retrieval information.

Abstract: A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.

Abstract: A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.