Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

Abstract: An electronic circuit includes a first transistor coupled between a first node and a supply voltage and controlled by a first node, a second transistor coupled between a second node and the supply voltage and controlled by the first node, a third transistor coupled between a third node and the supply voltage and controlled by a fourth node, a fourth transistor coupled between the fourth node and the supply voltage and controlled by the fourth node, a fifth transistor coupled between the first node and the fifth node and controlled by a reference voltage, a sixth transistor coupled between the second node and a ground and controlled by the third node, a seventh transistor coupled between the fourth node and the ground and controlled by the second node, a first resistor coupled the fourth node to the ground, and a second resistor coupled to the fifth node.

Abstract: A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

Abstract: A resonant half-bridge flyback power converter includes: a first transistor and a second transistor which form a half-bridge circuit; a transformer and a resonant capacitor connected in series and coupled to the half-bridge circuit; and a switching control circuit configured to generate a first driving signal and a second driving signal to control the first transistor and the second transistor respectively for switching the transformer to generate an output voltage. The first driving signal is configured to magnetize the transformer. The second driving signal includes at most one pulse between two consecutive pulses of the first driving signal. The switching control circuit generates a skipping cycle period when an output power is lower than a predetermined threshold. A resonant pulse of the second driving signal is skipped during the skipping cycle period. The skipping cycle period is increased in response to the decrease of the output power.

Abstract: A resonant switching power converter circuit including: a switching converter, a control circuit and a pre-charging circuit; wherein the control circuit controls a first switch of the switching converter in a pre-charging mode, so as to control electrical connections between a first power and at least one of plural capacitors of the switching converter, and to control other switches of the switching converter, so as to control the pre-charging circuit to charge at least one capacitor to a predetermined voltage; wherein in a start-up mode, the plural switches control electrical connections of the capacitors according to first and second operation signals, such that after the pre-charging mode ends, the switching converter subsequently operates in the start-up mode; wherein in the start-up mode, the first and second operation signals have respective ON periods, and the time lengths of the ON periods increase gradually.

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

Abstract: A foreign object detection method for detecting whether a foreign object exists on a function pin of a power supplier side or a power receiver side, wherein the power supplier side and the power receiver side are coupled to each other in a detachable fashion. The foreign object detection method includes: discharging a capacitor via the function pin, wherein the capacitor is electrically connected to the function pin; providing a sensing current flowing through the function pin, to charge the capacitor; sensing a voltage variation of the function pin during a predetermined period; and comparing the voltage variation with a predetermined variation, so as to determine whether a foreign object exists on the function pin.

Abstract: A scalable multi-phase switching converter includes: converter modules, each including: a loop control unit, which generates a basic trigger pulse according to a feedback signal in master operation mode; and a switching control unit, which determines an operation mode and a corresponding phase serial order according to a setting signal received by a setting pin in a setting mode, and generates a multi-phase trigger pulse signal at a trigger pin according to the basic trigger pulse in master operation mode. The switching control unit receives the multi-phase trigger pulse signal at the trigger pin in slave operation mode. The switching control unit generates an ON-trigger pulse according to the multi-phase trigger pulse signal and the corresponding phase serial order. An ON-period determination unit generates a conduction control pulse according to the ON-trigger pulse to control a corresponding inductor. The trigger pins of the converter modules are coupled to each other.

Abstract: A switching regulator includes a power stage circuit and a controller circuit. The controller circuit includes a first amplification circuit, a second amplification circuit, a ramp signal generation circuit, and a comparator. The first amplification circuit generates an amplification signal according to a difference between a low-pass filtered signal and a feedback signal. The second amplification circuit generates an adjustment signal according to a difference between the feedback signal and a fast response signal. The comparator generates a pulse width modulation signal according to a difference between the amplification signal and a ramp signal to generate a switch control signal. The adjustment signal adaptively adjusts the amplification signal or the ramp signal. The low-pass filtered signal is related to a signal generated by filtering out higher frequency part of the reference signal, and the reference signal is related to a dynamic change of a target level of the output voltage.

Abstract: A battery module for use in a battery system is operable in a bottom mode, a top mode or a middle mode during an enabled state. The battery module includes a battery unit and a battery control circuit. The battery unit which includes at least one battery generates a battery unit voltage between a positive terminal and a negative terminal of the battery unit. The battery control circuit is powered by the battery unit voltage and is configured to control the battery unit. The battery control circuit includes an enable terminal, an upstream input terminal, an upstream output terminal, a downstream input terminal, and a downstream output terminal. When the enable terminal is at an operation enabling level, or when the upstream input terminal is at an upstream enabling level, the battery module enters the enabled state.

Abstract: A power device which is formed on a semiconductor substrate includes: plural lateral insulated gate bipolar transistors (LIGBTs) and a forward conductive unit. The plural LIGBTs are connected in parallel to each other. The forward conductive unit is connected in parallel to the plural LIGBTs. The forward conductive unit consists of a PN diode and a Schottky diode connected in parallel to each other. The PN diode and the Schottky diode share a same N-type region, a reverse terminal, an N-type extension region, an field oxide region, a gate, and a P-type well in an epitaxial layer. The N-type region and the P-type well form a PN junction, wherein the PN junction has a staggered comb-teeth interface from top view. A metal line extends on the staggered comb-teeth interface and alternatingly contacts the N-type region and the P-type well.

Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

Abstract: A class-D amplifying system includes: a first digital-to-analog converter (DAC), a class-D amplifier circuit and a second DAC. The first DAC generates an analog input signal according to a digital input signal. The class-D amplifier circuit generates an output signal according to the analog input signal in a pulse width modulation (PWM) manner. The second DAC generates a common mode (CM) adjustment current for adjusting a CM voltage of the analog input signal according to one or more of the following parameters: (1) the CM voltage of the analog input signal; and/or (2) a driving power. A power stage circuit of the class-D amplifier circuit is powered by the driving power. The second DAC determines which parameter the CM adjustment current is correlated to according to: (A) A level state of the output signal; and/or (B) A level state of a PWM signal of the class-D amplifier circuit.

Abstract: A control circuit for controlling a power supply circuit to provide power to a system device which includes a communication circuit includes: a pulse width modulation (PWM) controller configured to switch a transformer of the power supply circuit to generate a first output voltage; and a switched capacitor converter configured to generate a second output voltage according to the first output voltage. The second output voltage provides power to the communication circuit, wherein the communication circuit generates a power saving signal to control the PWM controller and the switched capacitor converter. When the power saving signal is enabled, the first output voltage is decreased and a duty ratio of the switched capacitor converter is increased.

Abstract: A switched capacitor converter includes plural switch units. The switch units are configured to switch a coupling relationship of a capacitor between a first power and a second power, wherein at least one of the switch units includes a switch circuit. The switch circuit includes a first switch, a second switch, and a switch driving circuit, wherein the conduction resistance of the first switch is greater than the conduction resistance of the second switch, and the parasitic capacitance of the first switch is less than the parasitic capacitance of the second switch. The switch driving circuit turns on the first switch before the second switch is turned on and/or turns off the first switch after the second switch is turned off, such that the switching loss of the switch circuit is less than a predetermined target value.

Abstract: A power conversion circuit includes an N-level PWM power converter and a switching capacitor power converter. The N-level PWM power converter includes shared switches shared with the switching capacitor power converter, and PWM switches. In an N-level PWM mode, the shared switches and the PWM switches periodically switch an inductor and a capacitor, to execute power conversion between a first power and a second power by N-level PWM switching operation. The switching capacitor power converter includes the shared switches and auxiliary switches. In a capacitive conversion mode, the shared switches and the auxiliary switches periodically switch the capacitor, to execute power conversion between the first power and the second power by capacitive power conversion operation. In the capacitive conversion mode, a portion of the plural PWM switches are always OFF such that one end of the inductor is floating.

Abstract: A spread spectrum switching power converter circuit includes: a power stage circuit which includes an inductor and a power switch and is configured to switch the power switch according to a switching signal having spread spectrum for power conversion; a variable frequency oscillator, which generates a spread spectrum clock signal according to a spread spectrum control signal; a spread spectrum control circuit, which generates the spread spectrum control signal according to a first clock signal and a second clock signal; and a pulse width modulation circuit, configured to generate the switching signal according to a feedback signal based on the spread spectrum clock signal. The spread spectrum control circuit generates the spread spectrum control signal by sampling and combining a periodic waveform and a random waveform. The random waveform is generated according to the first clock signal and the periodic waveform is generated according to the second clock signal.

Abstract: A power conversion circuit includes a first and a second power converters for generating a first and a second driving voltages respectively. The second power converter is a switching converter. In a short-circuit detection mode, the first driving voltage is regulated to the first driving level, and the second power converter is configured to operate in a pulse frequency modulation mode to regulate the second driving voltage to a short-circuit detection level, and when a switching frequency of the second power converter exceeds a threshold frequency, a short-circuit condition between the second driving voltage and the first driving voltage is determined.

Abstract: A digital-to-analog converter (DAC) for generating an output voltage according to an input code includes a first-type and a second-type sub-DAC's connected in series. The first-type sub-DAC includes a first resistor string and plural first switches, and receives a reference current to determine a first voltage drop. The first switches are controlled by a first portion of the input code to determine a voltage division of the first voltage drop. The second-type sub-DAC includes a second resistor string and plural second switches. The second switches are controlled by a second portion of the input code to determine a portion of the second resistor string to receive the reference current, wherein the portion of the second resistor string and the reference current determines a second voltage drop. The output voltage includes a sum of the second voltage drop and the voltage division of the first voltage drop.

Abstract: A switched capacitor converter circuit includes: plural capacitors and plural switches which switch the connections of the plural capacitors periodically. In a first period, the plural switches control a first capacitor to be electrically connected between a first power and a second power, and control a second capacitor and a third capacitor to be electrically connected in series between the second power and a ground level. In a second period, the plural switches control the first capacitor and the second capacitor to be electrically connected in series between the second power and the ground, and control the third capacitor and the second capacitor to be electrically connected in parallel with the second power, thereby a second current of the second power is 4 times of a first current of the first power.