Abstract: A method for making a semiconductor device may include forming at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one nonsemiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Abstract: The invention relates to the field of grating structures. The invention provides a longitudinal grating having an aperiodic structure, wherein the grating has a selected response characteristic and any repeated unit cell in the structure is significantly longer than a characteristic length associated with the selected response characteristic.
Type:
Grant
Filed:
March 3, 2000
Date of Patent:
October 17, 2006
Assignee:
RJ Mears, LLC
Inventors:
Robert Joseph Mears, Michael Charles Parker
Abstract: A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Abstract: A semiconductor device may include at least one metal oxide field-effect transistor (MOSFET). The at least one MOSFET may include a body, a channel layer adjacent the body, and a dopant blocking superlattice between the body and the channel layer. The dopant blocking superlattice may include a plurality of stacked groups of layers. Each group of layers of the dopant blocking superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Abstract: A method for making a microelectromechanical system (MEMS) device may include providing a substrate, and forming at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Abstract: A method for making an integrated circuit may include forming at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Type:
Grant
Filed:
September 9, 2004
Date of Patent:
September 19, 2006
Assignee:
RJ Mears, LLC
Inventors:
Robert J. Mears, Robert John Stephenson
Abstract: A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
Type:
Grant
Filed:
November 18, 2004
Date of Patent:
July 4, 2006
Assignee:
RJ Mears, LLC
Inventors:
Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
Abstract: A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. At least one second region may be formed in the superlattice including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.
Type:
Grant
Filed:
April 1, 2005
Date of Patent:
May 16, 2006
Assignee:
RJ Mears, LLC
Inventors:
Robert J. Mears, Robert John Stephenson
Abstract: A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may further include at least one pair of oppositely-doped regions therein defining at least one semiconductor junction.
Type:
Grant
Filed:
April 1, 2005
Date of Patent:
May 16, 2006
Assignee:
RJ Mears, LLC
Inventors:
Robert J. Mears, Robert John Stephenson
Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.
Type:
Grant
Filed:
November 19, 2003
Date of Patent:
April 25, 2006
Assignee:
RJ Mears, LLC
Inventors:
Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
Type:
Grant
Filed:
November 18, 2004
Date of Patent:
April 25, 2006
Assignee:
RJ Mears, LLC
Inventors:
Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski
Abstract: A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may be formed by forming a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor.
Abstract: A method for producing aperiodic gratings and waveguides with aperiodic gratings uses a simulated annealing process that starts with a random configuration of grating elements and iteratively computes a spectral response from a Fourier transform of the configuration of grating elements obtained in successive iterations. A cost function is computed as a convergence criterion. The aperiodic grating can be used, for example, as a filter in WDM applications.
Type:
Grant
Filed:
October 10, 2003
Date of Patent:
January 31, 2006
Assignee:
RJ Mears, LLC
Inventors:
Robert J. Mears, Michael Charles Parker
Abstract: A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a high-K dielectric layer on the electrode layer, and forming an electrode layer on the high-K dielectric layer and opposite the superlattice.
Type:
Application
Filed:
May 25, 2005
Publication date:
January 26, 2006
Applicant:
RJ Mears, LLC
Inventors:
Robert Mears, Marek Hytha, Scott Kreps, Robert Stephenson, Jean Augustin Yiptong, Ilija Dukovski, Kalipatnam Rao, Samed Halilov, Xiangyang Huang
Abstract: A semiconductor device may include a semiconductor substrate and at least one active device adjacent the semiconductor substrate. The at least one active device may include an electrode layer, a high-K dielectric layer underlying the electrode layer and in contact therewith, and a superlattice underlying the high-K dielectric layer opposite the electrode layer and in contact with the high-K dielectric layer. The superlattice may include a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Type:
Application
Filed:
May 25, 2005
Publication date:
January 19, 2006
Applicant:
RJ Mears, LLC
Inventors:
Robert Mears, Marek Hytha, Scott Kreps, Robert Stephenson, Jean Augustin Chan yiptong, Ilija Dukovski, Kalipatnam Rao, Samed Halilov, Xiangyang Huang
Abstract: A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least one group of layers of the superlattice may be substantially undoped.
Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least one group of layers of the superlattice may be substantially undoped.
Abstract: A method for making a semiconductor device may include forming a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include performing at least one anneal prior to completing forming of the superlattice.
Type:
Application
Filed:
May 25, 2005
Publication date:
December 8, 2005
Applicant:
RJ Mears, LLC
Inventors:
Marek Hytha, Robert Stephenson, Scott Kreps
Abstract: A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
Type:
Grant
Filed:
August 22, 2003
Date of Patent:
October 25, 2005
Assignee:
RJ Mears, LLC
Inventors:
Robert J. Mears, Jean Augustin Chan Sow Fook Yiptong, Marek Hytha, Scott A. Kreps, Ilija Dukovski