Abstract: In a synchronized memory system comprising a memory controller externally coupled to a synchronous memory, a read valid loop back signal is introduced for the memory controller to track the delays of signals exchanged between the memory controller and the synchronous memory, so that the uncertainty introduced by I/O pads and PCB traces used to facilitate the coupling of the memory controller with the sychronous memory is no longer the limiting factor for the speed of the memory controller. An asynchronous FIFO buffer is used to latch read data returned by the synchronous memory based on the read valid loop back signal.

Abstract: A differential charge pump utilizing a common mode feedback circuit. The charge pump includes a dual reference current source and outputs a differential current signal by modifying currents routed to the outputs utilizing current paths having transistors maintained in the linear region within the current paths. The common mode feedback circuit includes differential transistors requiring a maximum power supply voltage of a common mode reference voltage plus a transistor threshold voltage.

Abstract: A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays.

Abstract: An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.

Abstract: A system and method for increasing test coverage of digital integrated circuits is provided. Clock trees are examined and circuits modified to provide for a greater number of flip-flops operating off of a positive clock edge as viewed from a clock origin.

Abstract: A method for sensing the concentrations of diatomic gases in a flow chamber is achieved by focusing an incident beam of light from a monochromatic light source on a point internal to the flow chamber through a transparent window. The incident excites molecules of the diatomic gas, resulting in emission of scattered light of particular characteristic frequency for each species of diatomic gas, due to the Raman principle. By collecting the scattered light beam from the flow chamber through the window and analyzing the intensity of the collected scattered beam at these characteristic frequencies, the relative concentrations of each of the diatomic gases may be determined.

Abstract: Copy protection is provided for the now-unprotected computer monitor port of a computer 100 in two ways: (i) delaying synchronizing signals by a time variable amount and (ii) generating pulses during non-active video. Delay of the synchronizing signal is performed by selecting a fixed offset 203 and selecting either the fixed offset of the pseudorandom delay to be sent to a variable delay generator 260, which delays the horizontal synchronizing signal 201 by the selected amount. This new delayed horizontal synchronizing signal 202 is encoded by the CRT Controller 244 and is then sent to the computer monitor 164, which uses the delayed synchronizing signal 202 as encoded to produce its display in conjunction with a data signal. Thus, if these signals 202, 268 are intercepted by a VGA to TV converter 122, the converter 122 (or any downstream device) is unable to lock onto the correct frequency in order to reproduce the image properly.

Abstract: A differential charge pump utilizing a common mode feedback circuit. The charge pump includes a dual reference current source and outputs a differential current signal by modifying currents routed to the outputs utilizing current paths having transistors maintained in the linear region within the current paths. The common mode feedback circuit includes differential transistors requiring a maximum power supply voltage of a common mode reference voltage plus a transistor threshold voltage.

Abstract: A differential charge pump utilizing a common mode feedback circuit. The charge pump includes a dual reference current source and outputs a differential current signal by modifying currents routed to the outputs utilizing current paths having transistors maintained in the linear region within the current paths. The common mode feedback circuit includes differential transistors requiring a maximum power supply voltage of a common mode reference voltage plus a transistor threshold voltage.

Abstract: A single rail domino logic circuit using a four-phase clocking scheme. A stacked PMOS pair provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement of an additional inverter in the output signal path to form both an output signal and a complement of the output signal for use in subsequent logic stages.

Abstract: A system and method for analyzing timing and noise effects in a hybrid circuit which contains a plurality of electrical components. The timing and noise effects for the hybrid circuit are generated by simulating electrical conditions within a hybrid circuit model. The hybrid circuit model is constructed by creating and integrating analog and behavioral models from the plurality of electrical components. The timing and noise effects remain accurate even at high printed circuit board/multi-chip module clock speeds, thereby ensuring that a user is able to construct an optimal design for any one of the plurality of electrical components.

Abstract: The present invention provides a buffer for coupling circuitry operating at a low voltage to circuitry operating a high voltage, and vice versa. The buffer outputs signals in a range between the low voltage and a ground voltage lower than the low voltage, and maintains appropriate bias of a semiconductor junction in the buffer using the high voltage. For example, the high voltage can be applied to the body of an output stage pull-up PFET of the buffer to maintain reverse bias between the body and drain of the PFET even when signals at the high voltage are placed on the drain of the PFET by other circuitry. Some embodiments of the present invention include a voltage translator to translate signals output from circuitry operating at the low voltage into a control signal at either the ground voltage or the high voltage. The high voltage of the control signal is beneficial for turning OFF an output stage transistor of the buffer even in the presence of signals at the high voltage on an output of the buffer.

Abstract: A system for adding or subtracting numbers in signed floating point notation performs exponent and mantissa handling operations in parallel. The system includes a comparator, for determining a greater-magnitude and a lesser magnitude floating point number, operating in parallel with a selector for performing a one's complement and single-bit shift on a mantissa portion of the lesser-magnitude floating point number. The system further includes a remaining shift circuit, for determining an additional amount by which the lesser-magnitude mantissa portion should be shifted; and a shifter. The system also includes an absolute add circuit, for determining whether an absolute addition or an absolute subtraction is to be performed, and a single-bit shift circuit, for indicating whether a shift of at least one bit is required.

Abstract: Aperture correction or edge detection circuitry filters input data for high-frequency components, and then selects areas most likely to be text based on the contrast of the signal and applying an amount of aperture correction responsive to the signal characteristics. A high pass filter (116) is employed to filter out low frequency components and separate the signal into positive and negative going transitions. Then, the positive-going signal is coupled to a contrast detector (124), which produces a control signal that controls the amount of aperture correction added to the signal by an aperture correction circuit 112. The contrast detector (124) is designed to generate an amount of aperture correction that is responsive to the high frequency content of the positive-going signal. In one embodiment, a global threshold is used that allows aperture correction to be applied to the input signal only if the amplitude of the high frequency component of the signal is greater than the threshold.

Abstract: An improved routing system and method allow routing of pluralities of signals to circuit blocks on integrated circuit chips using minimal die area. The improved routing system employs a plurality of tri-state buffers, a plurality of conductive lines, and a controller. The circuit block can be driven from remote locations via the tri-state buffers and conductive lines. The tri-state buffers are selectively enabled one at a time by the controller to prevent signal contention. The multiplexors encountered in conventional routing systems are not needed. The improved routing system and method are ideal for routing to and from large circuit blocks which have numerous terminals, such as embedded dynamic random access memory units, embedded static random access memory units, central processing units, arithmetic logic units, register files, and cores generally.

Abstract: An integrated circuit includes a first circuit module for generating a plurality of digital signals and a second circuit module for receiving the digital signals. A multiple input signature module receives the digital signals that are received by the second circuit module. The signature module generates and stores a signature value which is indicative of data values of the digital signals over a plurality of cycles. The signature module operates in response to control circuitry, which is responsive to a test signal, to cause the values indicative of the digital signals to be stored to the multiple input signature module, each time that valid signal values are received by the second circuit module. The multiple input signature module may be used for diagnostics by capturing data at a single, predetermined cycle. The module may be initialized to a predetermined value to ensure the signature value or, the single value captured, accurately reflects the data value of the digital signals.

Abstract: A dither unit preferably comprises an offset generator, an adjusted coordinate generator and a dither matrix. The offset generator is coupled to receive information about the relative position of the sub-sample being dithered, and in response generates offset values. The output of the offset generator along with the pixel coordinates are provided to the adjusted coordinate generator which generates adjusted coordinate values used by the dither matrix. The adjusted coordinate values along with a color value are received by the dither matrix, which in response, generates a dithered value for the sub-sample that can be stored back in the over sampling buffer for additional computation.