Abstract: The present invention provides an alpha blending unit that is able to perform alpha blending on sub-samples of a pixel in an efficient manner. The alpha blending unit preferably comprises a plurality of registers for storing a source color, a blending value, and a plurality of destination sub-sample values, multipliers, adders, an accumulator and a divider. The alpha blending unit advantageously sums the destination sub-sample values and then divides them by the number of sub-samples to generate a combined destination color value. This combined destination color value along with the source color and a blending value are then provided to the multipliers, and adders to generate a new destination color value for the pixel.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes selective pixel data fillers for writing either X or Y position pixel data to the internal SRAM devices. By selectively storing either X or Y position pixel data, the graphics processor is able to perform bit-block data transfers (blts) of pixel data to the internal SRAM thereby efficiently utilizing the local bandwidth of the internal SRAM.

Abstract: A write blocking accelerator provides maximum concurrency between a central processing unit (CPU) and the accelerator by allowing writes to the front buffer of a dual-buffered system. The CPU issues a series of drawing commands followed by a "page flip" command. When a command parser within the accelerator receives a page flip command, it notifies a screen refresh unit reading from the front buffer that the command was received. The screen refresh unit signals a memory interface unit (MIU) to enter a write blocking mode and provides the address of the current line in the front buffer from which the screen refresh unit is reading, and the address of the last line in the front buffer. The MIU blocks all writes from drawing engines that fall into the range defined between the two addresses. The screen refresh sends updated front buffer addresses to the MIU as display data is read out of the front buffer. Accordingly, the blocked address range constantly shrinks until all writes are allowed by the MIU.

Abstract: A display controller to upscale a source video image for display on a display unit of a computer system. An encoder circuit in the display controller chip stores in a local memory pixel data of previous scan lines required for interpolation in a compressed format using differential pulse code modulation (DPCM) scheme. A decoder circuit decompresses the pixel data into original format prior to sending to an interpolator. The interpolator receives a present scan line and the decompressed data of previous scan lines, and interpolates the received pixels to generate additional pixels required for upscaling the source video image.

Abstract: System and method transfer information from a primary processor to a co-processor. The primary processor includes an encoder, and the co-processor includes a decoder. To transfer information from the primary processor to the co-processor according to one embodiment of the present invention, the encoder in the primary processor creates an information word. An information word includes a plurality of bits, where each bit corresponds to a different type of information. The encoder sets the state of each bit to indicate whether information corresponding to that bit will be sent. The encoder then sends the information word, followed by the actual information. The decoder decodes the information word to determine what information will be arriving from the co-processor. The decoder identifies the information by the order in which it is received. Each different type of information is pre-assigned to a different register address in the co-processor.

Abstract: An arrangement for coupling a first packaged integrated circuit to a second packaged integrated circuit comprises a first packaged integrated circuit that includes a first set of electrical interconnection elements arranged on a first surface and a second set of electrical interconnection elements arranged on a second surface which is opposite to the first side. A thermally conductive material is disposed on the second surface and the second set of electrical interconnection elements are arranged around at least a portion of the periphery of the second surface. A second packaged integrated circuit includes a third set of electrical interconnection elements arranged on a first surface of the second packaged integrated circuit. The third set of electrical interconnection elements are shaped to mechanically and electrically couple and decouple to or from the second set of electrical interconnection elements non-destructively by application of manual force.

Abstract: An improved method and apparatus for rendering curved surfaces in a graphics system. The appearance of a curved surface is created by varying color shades across an object. The graphics systems represents each primary color with fewer than eight bits. The present invention maintains smooth transaction between color shades despite using fewer than eight bits to represent color. An eight bit color shade value is truncated, with the most significant bits being saved and used as a color value. The least significant bits that are truncated are used to determine which of the adjacent color values to use to render pixels. Thus, if five bits are saved and used to represent a color, the three least significant truncated bits are used to determine the appropriate mix of the closest five bit shades. The three truncated bits are used to select an entry from a ramp table and a control signal from a look-up table selects a bit from the selected ramp table entry.

Abstract: An analog joystick interface system for overcoming the deficiencies of the conventional analog joystick interface by supporting positional tracking in both a legacy and an enhanced mode. In the legacy mode, the host calculates the relative physical orientation of a positional grip of an analog joystick by relying upon continuous polling techniques. In the enhanced mode, a watch dog timer relieves the host of the need to continuously poll by directly providing the host with positional data concerning the relative physical orientation of the positional grip. The ability of the joystick interface to provide both the legacy and enhanced modes ensures that compability issues concerning the legacy DOS-based software applications and CPU allocation problems associated with continuous polling are resolved without considerably increasing cost or complexity of the joystick interface.

Abstract: A device performs both 2-tap and 3-tap flicker filtering of non-interlaced lines of computer graphics data to form interlaced lines. The device includes a data packer, a data unpacker, and a filter circuit. The filter circuit combines lines that it receives to form filtered lines. The data packer writes the filtered lines to line buffers while the data unpacker reads the lines stored in the line buffers. The read lines are either sent to the filter circuit for further filtering or are outputted to be displayed as interlaced lines. Both 2-tap and 3-tap flicker filtering can be accomplished by varying the order and/or number of read, write, and filter operations.

Abstract: A tunable digital oscillator circuit comprises a first dual-clock pulse generator, a second dual-clock pulse generator, a run controller, a stop controller and a decoder. The first and second dual-clock pulse generators are coupled in a cascaded manner with the output of the first dual-clock pulse generator provided as an input to the second dual-clock pulse generator. Each of the first and second dual-clock pulse generators is preferably tunable, in that, they can output one clock signal from a predetermined number of frequencies. The run controller is preferably coupled to receive a start signal and the output of the second dual-clock pulse generator. The run controller provides the input to begin and maintain the first and second dual-clock pulse generators in the state of generating a clock signal. The stop controller is coupled to receive a clock signal from the first dual-clock pulse generator, and a stop signal. The tunable digital oscillator circuit can start or stop the clock within two clock cycles.

Abstract: The improved pin system enables a single, shared pin of a semiconductor device to have multiple functions that include: receiving data that determines the operating mode of the semiconductor device and also receiving data unrelated to the operating mode of the semiconductor device. The improved pin system comprises the single, shared pin coupled to a data latch. The data latch is configured to store operating mode data from the single, shared pin. This operating mode data preferably corresponds to a particular operating mode such as a functional mode or a test mode. Preferably, in response to the operating mode data stored in the data latch, the semiconductor device operates in either the functional mode or the test mode. As long as the data latch stores the operating mode data, this shared, single pin is capable of receiving data unrelated to the operating mode of the semiconductor device without changing the current operating mode of the semiconductor device.

Abstract: A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be to transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a shortened display list. A host processor generates a display list which includes a field load instruction for loading the display list into a register file. The graphics processor includes logic to encode and decode the field load instruction thereby shortening the display list loaded into the register file. The field load instruction may also be decoded to allow the graphics processor to randomly load the register file thereby shortening the processing of the display list.

Abstract: A data stream accessed in a sequential manner is stored in a plurality of pages in a main memory of a computer system. The pages are contiguous in virtual memory but not in physical memory. The page address translation entry needed to translate the virtual address of a next page into a physical address is embedded in the current page of the data stream. A peripheral processor coupled to the main memory by a bus accesses the data stream by reading the page address translation entry of the first page of the data stream, reading the page addressed by the physical address resulting from the page address translation entry, obtaining the next page address translation entry by extracting it from the current page without performing a read operation of the bus, and reading the next page addressed by the physical address resulting from the extracted page address translation entry.

Abstract: A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an internal memory and/or an external display memory. Each MPRB comprises a plurality of addressable storage location holding video data and linked in a logical ring configuration. In addition, each MPRB has at least three ports, selected from write ports for writing to the addresses of the storage locations and read ports for reading from the addresses. Each read port in the MPRB is disposed a certain distance, or number of storage locations, behind a write port. This distance defines the size of the memory emulated by the MPRB. By positioning multiple read ports at different distances from the write ports, a single MPRB can emulate several different memories of different sizes.

Abstract: A multi-function controller in a computer graphics system performs the functions of a graphics processor, a video processor, a system memory controller, a cache controller, and a PCI bridge. The multi-function controller is connected to the host bus of the computer graphics display system to maximize performance. A graphics frame buffer and a system memory are combined into a unified system memory, which is controlled by and coupled to the multi-function controller.

Abstract: A method for sensing the concentrations of diatomic gases in a flow chamber is achieved by focusing an incident beam of light from a monochromatic light source on a point internal to the flow chamber through a transparent window. The incident excites molecules of the diatomic gas, resulting in emission of scattered light of particular characteristic frequency for each species of diatomic gas, due to the Raman principle. By collecting the scattered light beam from the flow chamber through the window and analyzing the intensity of the collected scattered beam at these characteristic frequencies, the relative concentrations of each of the diatomic gases may be determined.

Abstract: A processor having a sliceable architecture wherein a slice is the minimum configuration of the processor datapath. The processor can instantiate multiple slices and each slice has a separate datapath. The total processor datapath is the sum of the number of slices multiplied by the width of a slice. Accordingly, all general purpose registers in the processor are as wide as the total datapath. A program executing on the processor can determine the maximum number of slices available in a particular processor by reading a register. In addition, a program can select the number of slices it will use by writing to a different register. The processor replicates control signals for each active slice in the processor and supports instructions for transferring data among the slices. Furthermore, the processor supports a set of instructions for fetching and storing data between multiple slices and the memory.

Abstract: The present invention provides improved output buffers for use on IC Chips. These output buffers incorporate a compensation circuit for compensating the performance characteristics of transistors included in the output buffers. The compensation circuit determines whether the output buffer is operating at a desired slew-rate. In response to this determination, the compensation circuit supplies a compensation voltage or voltages. The compensation voltages control a variable quantity of power delivered by a voltage controlled power source (VCPS). By increasing or reducing this power, the slew-rate of the output buffers are respectively increased or reduced. The compensation voltages maintain this slew-rate within narrow tolerances. This allows the improved output buffers of the present invention to meet very narrow input tolerances of circuitry coupled to receive signals from the IC Chip.

Abstract: A graphics processing system incorporates a calibrator module into the system. As a memory module continuously transmits a model data signal, the calibrator module automatically increments the number of stages of delay, which are integrated into a delayed clock signal. Each delayed clock signal triggers the sampling of the model data signal by a plurality of latches. The calibrator module compares each of these sampled data signals with the original model data signals. If the delayed clock signal is properly aligned with the model data signal to cause the two signals to match, the calibrator module stores a result signal in a "1" logic state. If the delayed clock signal is misaligned with the model data signal, the calibrator module will store the result signal in a "0" logic state.