Abstract: A data capture system includes a data early latch, a data on-time latch, and a data late latch each coupled to receive an input data signal and a first, second, and third data strobe signal, respectively. When the respective data strobe signal is triggered the respective data latch captures, or latches, the input data signal at three intervals resulting in oversampled input data signals. The on-time data latch generates the latched data signal. The latched data signal is compared with the data early signal latched by the data early latch as well the data late signal latched by the data late latch. If the latched data signal and the data early signal are not equal, a delay controller increases the delays of the data strobe signals. If the latched data signal and the data late signal are not equal, the delay controller decreases the delays of the data strobe signals.

Abstract: A system and method for traversing and rendering a graphic primitive represented in screen space, employing block- and band-oriented traversal algorithms in texture mapping. Improved performance is achieved through burst-mode texture access and texture caching in connection with a texture map subdivided into squares. Block- and band-oriented traversal facilitates minimization of page breaks and texture cache swap-out. Improved determinism is facilitated by obviating the need for pixel sorting algorithms. Improved re-use of retrieved data segments in burst-mode access is facilitated.

Abstract: A multiplier array is modified to perform interpolations. The interpolations use a normalized first operand A between 0 and 1. The interpolation is the function B * A+C * (1-A). Standard multipliers accept two operands as inputs, but interpolations require 3 operands (A, B, C). The AND gates in Booth encoders in a standard multiplier array are replaced by multiplexers. Each multiplexer selects a bit from one of the two operands (B or C) based on a bit of the first operand A. The interpolate operation multiplies the first operand A by the second operand B while simultaneously multiplying the bit-wise inverse of the first operand A' by the third operand C. Since one multiply is with the first operand A while the second multiply is with the inverse A' of the first operand, one of the multiplies always generates zero while the other multiply generates either a one or a zero for each bit of the first operand.

Abstract: A graphics display system processes text data in a video signal, preferably in the vertical blanking interval, and allows a user to selectively display the text data in real time, search the text data, or obtain a transcript of the data. A digitizer and decoder circuit extracts the text data from a video signal and adds an identifier to the text data. A graphics user interface accelerator stores the text data. Concurrent with adding the identifier and the storage of the text data, the digitizer and decoder circuit adds an identifier to the video and audio data, and the graphics user interface accelerator stores the video and audio data. The identifier added to the video and audio data links such data to the associated text data. In response to a user search request, a host processor scans the stored text data for text data that matches a user selected input, and retrieves the text data matching the user selected input.

Abstract: A method and apparatus for correcting the flicker artifact associated with noninterlaced to interlaced video conversion includes a Set-Interpolative-Threshold comparator function whereby weighted line averaging is used only if the difference in luminance, or other color component, of vertically adjacent pixels in the noninterlaced video exceeds a user set threshold value. When the differential value in luminance, or other color component, is greater than the threshold value, and such line averaging is used, the negative effects of the line averaging, such as blurring and darkening of the resulting video frame, are at least partially corrected by aperture/inverse aperture correction.

Abstract: A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit.

Abstract: A voltage tolerant bus hold latch comprises a first buffer transistor, a sense transistor, a low voltage latch, a node voltage controller and a pull-up circuit. The low voltage latch is coupled to the input by the first transistor. The node voltage controller is coupled to the input by the sense transistor. The node voltage controller has a pair of additional inputs coupled to the output of the low voltage latch. The output of the node voltage controller is coupled to control the operation of the pull-up circuit. The pull-up circuit is coupled to the supply voltage for the lower voltage circuitry, and has another control input coupled to the output of the low voltage latch. The output of the pull-up circuit is coupled to the input of the voltage tolerant latch. The pull-up circuit is selectively activated to pull the input of the latch to a high voltage level.

Abstract: A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an internal memory and/or an external display memory. Each MPRB comprises a plurality of addressable storage location holding video data and linked in a logical ring configuration. In addition, each MPRB has at least three ports, selected from write ports for writing to the addresses of the storage locations and read ports for reading from the addresses. Each read port in the MPRB is disposed a certain distance, or number of storage locations, behind a write port. This distance defines the size of the memory emulated by the MPRB. By positioning multiple read ports at different distances from the write ports, a single MPRB can emulate several different memories of different sizes.

Abstract: Disclosed is a system and method for mixing a plurality of graphics and video signals to create a desired output format, the desired output format being a mixture of the received signals. The mechanisim for achieving this rich format is a multi-modal graphics video overlay controller. The controller having a set of opcodes, selects a subset of the opcode set, this selection being a function of a desired output format of the mixed signals. The subset of opcodes is then utilized to control the means for selectively switching among the received graphics and video signals to create the desired output format. The selective switching is accomplished on a pixel by pixel basis.

Abstract: A graphics display system processes a video signal that includes closed caption text. A digitizer and decoder circuit retrieves the closed caption data and formats the data to avoid loss by decimation, to be scalable, and to include an indicator of capture or display. The digitizer and decoder circuit includes ping pong buffers for storing the data. During a first odd field, the closed caption data is stored in the ping buffer and the closed caption data from a previous field is read from the pong buffer. During the even field, the closed caption data is again read from the pong buffer. During the next odd field, the operation is repeated with the functions of the ping and pong buffers reversed. Alternatively the even field may contain the closed caption data. The digitizer and decoder circuit includes a capture or display valid bit in the closed caption data to indicate that the caption data is from the current field.

Abstract: In a computer controlled graphics system, processes are provided for detecting errors incurred in a display list having variable length instruction/parameter (I/P) sets, the errors occurring during parameterization, transmission, branching, and storage of the display list. Each process includes generating a display list including I/P sets, each I/P set including n parameter words following an instruction word. In each embodiment, a display list is encoded, transmitted, stored in a memory unit, and verified. In one embodiment, the display list is encoded by storing into each instruction word of each I/P set a parity bit of a value representative of the parity of the whole I/P set. In another embodiment, the display list is encoded by storing within each instruction word of each I/P set an m-bit checksum value. The m-bit checksum value is generated by partitioning each I/P set into y m-bit partitions which are summed, ignoring overflow.

Abstract: A transformerless data access arrangement (DAA) device facilitates data transfer between a high speed modem device and a central office telephone line (i.e., a phone line). The DAA device uses D/A and A/D converters in conjunction with a pair of nonlinear opto-couplers that function as an isolation barrier. The A/D converter converts an analog signal received from the phone line into a one-bit modulated digital signal. The digital signal is relayed by the nonlinear opto-couplers to a processor. Since the relayed signal is digital, the use of nonlinear opto-couplers does not result in unacceptable levels of noise and distortion. This is relevant since high speed modems have stringent noise and distortion requirements. A phone line supply voltage is regulated internally and used to power the DAA device. When the processor detects a ring signal on the phone line, the processor generates a control signal which places the A/D and D/A converters in idle mode while sending a caller ID directly to the processor.

Abstract: A universal input/output buffer uses all digital-type components, can be included on an integrated circuit chip and operates in a mixed voltage, multi-rail, power supply environment. The input/output buffer includes a multi-stage driver section and a sequencing section. Several types of sequencing techniques are used to control a plurality of driver stages and provide a combination of multiple firing schemes. In addition, other control techniques are employed such as full and partial feedback, sequential turn on/turn off of driver stages, and controlled introduction of a small amount of "crow bar" current.

Abstract: An integrated circuit includes a controller and a memory to implement a graphics controller. The controller and memory are controlled by a common clock signal to operate synchronously with each other. The memory is organized in a plurality of storage arrays, organized in two banks. A set of bit-line sense amplifiers is provided for each bank. A pair of row decoders decode a row address to select a row of data from each bank. The selected row of data is received by a pair of bit-line sense amplifiers. A column decoder selects a column of data from the pair of bit-line sense amplifiers. A pair of multiplexers select one-half of the selected column in response to a HI/LO signal and then select the remaining half of the selected data in response to a change in value of the HI/LO signal. Main or data sense amplifiers amplify the output of the multiplexers to provide data outputs in the form of full swing signals.

Abstract: An adder system includes at least one adder block subsystem. Each adder block subsystem includes a pair of input signal lines, an adder circuit block having a conditional sum-select and a conditional carry-select, a sum-high line, a sum-low line, a carry-high line, carry-low line, a sum selection switch, a carry selection switch, a carry forward line, and an output signal line. The input lines are individual bit lines that are paired together from the least significant bit to the most significant bit. Within the adder circuit block, pairs of the input bit lines are coupled to the conditional sum-select and the conditional carry-select. The conditional sum-select is coupled to the sum-high and sum-low lines and the conditional carry-select is coupled to the carry-high and carry-low line. The sum selection switch selectively couples the output signal line to the sum-high or the sum-low line.

Abstract: A system and method for reordering memory references for pixels to improved bandwidth and performance in texture mapping systems and other graphics systems by improving memory locality in conventional page-mode memory systems. Pixel memory references are received from a client graphics engine and placed in a pixel priority heap. The pixel priority heap reorders the pixel memory references so that references requiring a currently open page are, in general, processed before references that require page breaks. Reordered pixel memory references are transmitted to a memory controller for accessing memory.

Abstract: A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Several trace records from different processor cores can be rapidly generated and loaded into the debug queue. The external interface cannot transfer these trace records to an external in-circuit emulator (ICE) at the rate generated. The debug queue transfers trace records to the external ICE using a dedicated bus to the ICE so that bandwidth is not taken from the memory bus. The memory bus is not slowed for debugging, providing a more realistic debugging session. The debug buffer is also used as a video FIFO for buffering pixels for display on a monitor. The dedicated bus is connected to an external DAC rather than to the external ICE when debugging is not being performed.

Abstract: The system and method of the present invention performs an iterative operation that subdivides selected polygons (e.g., triangles) having high perspective ratios into a plurality of smaller polygons to limit artifact creation during the rendering/texture map processes. The present invention is particularly well suited for interpolation driven rendering/texture map processes. Processing logic of the present invention analyzes each polygon stored in display list memory of a graphics accelerator or graphics subsystem and determines a perspective ratio between adjacent vertices of the polygon. If the perspective ratio is greater than a pre-selected limit, the edge bounded by the vertices is subdivided at the mid-point and new polygons are created. The process is iterative until all polygons have perspective ratios that are less than the pre-selected limit, at which time the object data can be displayed by the hardware.

Abstract: A compositing buffer having an adjustable size and configuration reduces complexity and size of a multimedia processor integrated circuit. The compositing buffer may be optimized for lower resolutions, thus reducing its overall size and complexity, while still providing support for higher resolutions which may be required to support a particular standard. A pixel mapping logic receives data indicating the number of lines per band and number of pixels per line, as well as color depth (or any two of these data) and correctly maps compositing RAM bank access requests to the correct pixel location. In a second embodiment of the present invention, the variable band size of the compositing buffer may allow for an external memory to be used for a compositing buffer, for example, a portion of the display memory (frame buffer). While such an embodiment may reduce overall bandwidth, the associated cost reduction may make such an apparatus appealing for low cost applications.

Abstract: A method and apparatus is disclosed for reading display data from the same area in display memory and processing the display data as video pixel data or graphics pixel data depending on the state of at least one tag bit stored with the data. The apparatus receives display data from display memory, separates at least one tag bit from the display data and uses at least one tag bit in a controller to enable processing display data as video pixel data or graphics pixel data in each processing step. Video pixels may be corrected for missing color components with stored value if previous or next pixel in pipeline is graphics. Display memory and display memory bandwidth may be conserved by enabling video pixel data formats and graphics pixel data formats to be stored within the same display memory area.