Abstract: According to an embodiment, an electronic device includes a memory, a first processor coupled to the memory and configured to control the electronic device in a normal execution environment (REE), and a second processor coupled to the memory and configured to control the electronic device in a secure execution environment (TEE). The first processor in the REE may be configured to transfer, to the second processor in the TEE, a request for generating a block including verification data of a data chunk. The second processor may be configured to generate the verification data of the data chunk by using key information of the electronic device, sign the verification data, and transmit, to an external electronic device, the block including the signed verification data.

Abstract: An electronic apparatus for controlling a robot cleaner and an operation method thereof. The electronic apparatus that obtains position information, by using a wireless communication interface, based on at least one of a position of a position tracking tag device, a position of at least one home appliance located around the robot cleaner, and a relative position between the robot cleaner and the electronic apparatus, determines a target cleaning region based on the obtained position information, and transmits information about the determined target cleaning region to the robot cleaner.

Abstract: There is provided a storage device, which includes: a memory device that includes a plurality of memory blocks, and stores first meta data including first status data and a first parameter in a first memory block among the plurality of memory blocks; and a memory controller that stores second meta data including second status data and second parameters, determines final meta data among a plurality of pieces of meta data including the first meta data and the second status data by comparing a plurality of pieces of status data with the first status data and the second status data, performs parameter confirmation for storing the final meta data in the meta block, and controls the memory device based on a parameter stored in the meta block.

Abstract: A convolutional neural network (CNN) processing method includes selecting a survival network in a precision convolutional network based on a result of performing a high speed convolution operation between an input and a kernel using a high speed convolutional network, and performing a precision convolution operation between the input and the kernel using the survival network.

Abstract: A storage controller configured to control a nonvolatile memory includes a one-time programmable (OTP) memory configured to store a first public key, and a processor configured to, based on a first signature added to a firmware image including a host authentication public key being verified using the first public key, receive a storage command including at least one second public key and a first host authentication signature for the at least one second public key and store the at least one second public key in the OTP memory based on the first host authentication signature being verified using the host authentication public key.

Abstract: An electronic apparatus and a controlling method thereof are provided.

Abstract: An apparatus includes one or more processors configured to generate a plurality of feature maps having respective different resolutions based on an input image; and update, for each of the plurality of transformer layers, respective position estimation information comprising first position information of a respective bounding box corresponding to one object query and second position information of respective key points corresponding to the one object query, wherein each of the plurality of transformer layers includes a self-attention model configured to generate respective intermediate data by performing self-attention on respective content information on a feature of the input image; and a cross-attention model configured to generate respective output data by performing cross-attention on respective one or more feature maps among the plurality of feature maps and the respective generated intermediate data.

Abstract: A processor-implemented method includes generating an adjusted reference patch by adjusting a position of a reference patch in a reference image based on a pixel value of a ground truth (GT) patch of a GT image and a pixel value of the reference patch, wherein the GT patch corresponds to a specific region of an input image; generating a super-resolution (SR) image of the input image using a SR model provided an input that is based on the generated adjusted reference patch; and training the SR model based on the SR image and the GT image.

Abstract: A method of optimizing a quantization step size of an analog-to-digital converter (ADC) based on a number of crossbar arrays of a computing device includes: generating a first mapping relationship between the quantization step size of the ADC and a first root mean square error, the first root mean square error reflecting a quantization error and a clipping error, wherein the generating the first graph is based on use of only a single crossbar array; generating a second mapping relationship between the quantization step size of the ADC and a second root mean square error, the second root mean square error reflecting a quantization error, wherein the generating the second mapping is based on a uniform distribution of a total sum of quantization errors; and determining the quantization step size of the ADC based on the first mapping relationship and the second mapping relationship.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A multi-display device includes a plurality of display modules. At least one display module of the plurality of display modules includes: a receiver to receive first video data and first control data from another display module connected to a front stage, from among the plurality of display modules, or an external input device; one or more processors to obtain, from the first video data, a first area corresponding to video data that the at least one display module displays; and a merger to: allocate, to the first area, second control data including remaining control data of the first control data other than control data of the first control data to control the at least one display module, and merge the second control data with second video data including remaining video data of the first video data other than video data of the first video data that the at least one display module displays.

Abstract: Some example embodiments provides a display device including: a display panel on which a plurality of data lines are positioned; a source driver including a plurality of output switches connected to the plurality of data lines and supplying a plurality of data signals to the plurality of data lines during a period in which the plurality of output switches are turned on by an output control signal; and a source control circuit that differently controls an on-slew rate of the output control signal for each of a plurality of display areas of the display panel according to a distance between each display area and the source driver.

Abstract: According to an embodiment of the disclosure, a method for editing avatar model based on language-driven, the method comprising: receiving a first input including language description, obtaining a first latent vector based on the first input, updating an initial avatar model to a first three-dimensional avatar model based on the first latent vector, displaying the first three-dimensional avatar model.

Abstract: A semiconductor package includes a first semiconductor chip including a circuit layer on a first substrate, first through silicon vias passing through the first substrate, first lower bump pads on the circuit layer, and a first upper bump pad and a second upper bump pad on a second surface of the first substrate, each of the first upper bump pad and the second upper bump pad connected to a corresponding one of the first through silicon vias. The package includes a second semiconductor chip including a circuit layer on a first surface of a second substrate, and second lower bump pads on the circuit layer on the second substrate. The package includes a first solder bump to bond the first upper bump pad and the second lower bump pad, and a plurality of second solder bumps to bond the second upper bump pad and the second lower bump pads.

Abstract: An electronic device using a spatio-temporal self-similarity (STSS) and a method of operating the electronic device are disclosed. The electronic device may generate an STSS tensor including a spatial self-similarity map and spatial cross-similarity maps for each position of a video feature map corresponding to an input video based on a temporal offset and a spatial offset. STSS feature vectors may be generated from the STSS tensor by decreasing a dimension of the spatial offset and maintaining a dimension of the temporal offset for each position of the STSS tensor. An STSS feature map may be generated by integrating the dimension of the temporal offset for each position of the STSS feature vectors. An inference on the input video may be based on a result of adding the STSS feature map to the video feature map.

Abstract: The present disclosure provides apparatuses and methods for operating a flash memory for programming operating system (OS) data before an surface mount technology (SMT) process. In some embodiments, the method includes erasing a plurality of memory cells in a memory block, reducing a lateral charge loss of the plurality of memory cells due to high temperature degradation during the SMT process by applying a pre-program voltage to word lines coupled to the memory block, and performing multi-bit programming of the OS data in the plurality of memory cells, prior to performing the SMT process. The applying of the pre-program voltage causes threshold voltages of the plurality of memory cells to increase.

Abstract: Disclosed is an electronic device including a housing structure including a hinge, a first housing connected to the hinge, a first surface and a second surface oriented in a direction opposite to the first surface, a second housing connected to the hinge. The second housing may include a sensor, a third surface and a fourth surface oriented in a direction opposite to the third surface, the first surface facing the third surface in a folded state, and the first surface and the third surface being oriented in a same direction in an unfolded state, a first display provided over the first surface and the third surface.

Abstract: A semiconductor device includes a semiconductor die, a detection structure, a path control circuit and a detection circuit. The semiconductor die includes a central region in which a semiconductor integrated circuit is provided and an external region surrounding the central region. The detection structure is provided in the external region. The path control circuit includes a plurality of switches that controls electrical connection of the detection structure. The detection circuit determines whether a defect is present in the semiconductor die and a location of the defect based on a difference signal. The difference signal corresponds to a difference between a forward direction test output signal and a backward direction test output signal obtained by propagating a test input signal through the detection structure in a forward direction and a backward direction, respectively, via the path control circuit.

Abstract: An apparatus including a processor configured to execute a plurality of instructions; and a memory storing the plurality of instructions, wherein execution of the plurality of instructions configures the processor to generate a defect prediction score of an input image through the use of a neural network provided reference image, the input image, and an enhanced image. The neural network may include an attention map modulator configured to adaptively adjust an intensity of an attention map generated during the use of the neural network.

Abstract: A semiconductor package includes a substrate including a substrate pad and plural vias, the substrate having a first trench on a top surface of the substrate, and a chip stack on the substrate that includes semiconductor chips. A chip pad of a first semiconductor chip, which is a lowermost one of the semiconductor chips, is bonded to the substrate pad of the substrate. The chip pad and the substrate pad are formed of a same metallic material. The first trench overlaps with a corner of the first semiconductor chip, when viewed in plan view.