Abstract: A waveguide and an augmented reality (AR) device employing the waveguide are disclosed. The waveguide includes a waveguide body, an input-coupling element inputting a light into the waveguide body, a reflective element disposed at one side of the waveguide body and again inputting a light that is not input into the waveguide body or is transmitted through the waveguide body into the waveguide body, and an output-coupling element outputting a light propagating inside the waveguide body to an outside.

Abstract: An augmented reality (AR) device is provided. The AR device includes a display configured to output light of a first polarization; a polarization-conversion reflector provided opposite to an output side of the display, the polarization-conversion reflector converting the light of the first polarization into light of a second polarization that is orthogonal to the first polarization and reflect the light of the second polarization; a waveguide having a flat plate shape, a normal line of a flat surface of the flat plate shape being inclined with respect to an optical axis of the light of the first polarization output from the display, a side of the waveguide being provided between the display and the polarization-conversion reflector; an input-coupler inputting the light of the second polarization into the waveguide; and an output-coupler outputting light propagating in the waveguide.

Abstract: A method with global localization includes: extracting a feature by applying an input image to a first network; estimating a coordinate map corresponding to the input image by applying the extracted feature to a second network; and estimating a pose corresponding to the input image based on the estimated coordinate map, wherein either one or both of the first network and the second network is trained based on either one or both of: a first generative adversarial network (GAN) loss determined based on a first feature extracted by the first network based on a synthetic image determined by three-dimensional (3D) map data and a second feature extracted by the first network based on a real image; and a second GAN loss determined based on a first coordinate map estimated by the second network based on the first feature and a second coordinate map estimated by the second network based on the second feature.

Abstract: A variable resistance memory device includes active regions apart from each other, common bit line contacts in the active regions, first active source contacts on first active regions near one edge of each of the common bit line contacts, second active source contacts on second active regions near another edge of each of the common bit line contacts, word lines between the first active source contacts and the common bit line contacts and between the common bit line contacts and the second active source contacts, bit lines on the common bit line contacts, variable resistance layers connected to the second active source contacts, the word lines, and the bit lines, spin-orbit torque (SOT) layers connected to the first active source contacts on the variable resistance layers, the word lines, and the bit lines, source line contacts on the SOT layers, and source lines connected to the source line contacts.

Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS2) substrate.

Abstract: Disclosed is a method and apparatus for testing a liveness, where the liveness test method includes receiving a color image and a photodiode (PD) image of an object from an image sensor comprising a pixel formed of a plurality of PDs, preprocessing the color image and the PD image, and determining a liveness of the object by inputting a result of preprocessing the color image and a result of preprocessing the PD image into a neural network.

Abstract: A water purifying filter assembly including a filter case including a receiving member having a protrusion; and a head assembly. The protrusion may be configured to be receivable in a recessed portion on an outer circumferential surface of a filter so that when the filter is placed in the receiving member with the protrusion received in the recessed portion, the filter is fixedly couplable to the head assembly by rotation of the filter, and when the filter is placed in the receiving member with the protrusion not received in the recessed portion, the filter is prevented from being fixedly couplable to the head assembly.

Abstract: A window assembly includes a transparent window layer and a first coded mask layer provided on a first surface of the window layer, the first coded mask layer having a first shape configured to change a first property of light passing through the window assembly. The first coded mask layer may include a meta-surface including a phase modulation meta-pattern. The meta-surface may further include an amplitude modulation meta-pattern. A second coded mask layer having a second shape configured to change a second property of the light passing through the window assembly may further be provided on a second surface of the window layer.

Abstract: A clock data recovery circuit includes an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal, a sampler circuit configured to sample input data based on the first clock pair and the second clock pair, and a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit, the I-Q merged phase interpolator circuit is configured to share analog inputs based on the control signal.

Abstract: A method of manufacturing an integrated circuit (IC) device including forming an etching target structure on a substrate, forming an etching mask pattern having an opening on the etching target structure, etching a portion of the etching target structure through the opening to form a first hole in the etching target structure, forming a conductive polymer layer to cover the etching target structure inside the first hole, and etching another portion of the etching target structure through the first hole, in a state in which the etching target structure is covered by the conductive polymer layer inside the first hole, to form a second hole in the etching target structure and extending from the first hole toward the substrate may be provided.

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

Abstract: Provided is a light detection and ranging (LiDAR) device including a housing including a window configured to transmit light, a light transmitter provided in the housing and configured to output light toward an object outside of the housing, an optical element provided adjacent to the window, first light from among the light being incident on the optical element, a light receiver provided in the housing and configured to receive, from among the light, second light reflected from the object, and a processor configured to change a steering direction of the light such that a ratio of the first light to the light is reduced.

Abstract: A semiconductor device includes a first gate electrode and a second gate electrode which are each on a substrate and extend in a first direction, first and second source/drain patterns spaced apart from the first and second gate electrodes in a second direction which crosses the first direction, and an active contact in common connection with top surfaces of the first source/drain pattern and the second source/drain pattern. The active contact comprises a first portion on the first source/drain pattern and a second portion on the second source/drain pattern. The device includes an insulating separation pattern which extends in the second direction to separate the first gate electrode from the second gate electrode, and the active contact comprises a third portion which extends to a region below a bottom surface of the insulating separation pattern to connect the first and second portions of the active contact to each other.

Abstract: Provided are an optical device which is capable of optically implementing an activation function of an artificial neural network and an optical neural network apparatus which includes the optical device. The optical device may include: a beam splitter splitting incident light into first light and second light; an image sensor disposed to sense the first light; an optical shutter configured to transmit or block the second light; and a controller controlling operations of the optical shutter, based on an intensity of the first light measured by the image sensor.

Abstract: An electronic device according to various embodiments may include a communication interface configured to be electrically connected to at least one communication device establishing a communication channel with a mobile terminal and a processor, wherein the processor may be configured to identify a plurality of communication channels for performing data exchange through a plurality of wireless communications supported by the mobile terminal, identify one of a capacity of the plurality of communication channels or a precision of the plurality of communication channels, and determine a communication channel to be used for determining a location of the mobile terminal, based on an identification result. The plurality of communication channels may include at least two channels for performing data exchange through different types of wireless communication.

Abstract: Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.

Abstract: A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.

Abstract: A server for predicting a future traffic load of a base station is provided. The server may obtain a first prediction model based on traffic data collected from the base station for a first period of time, obtain a second prediction model based on traffic data collected from the same base station for a second period time, and also based on knowledge transferred from the first prediction model. Each of the first prediction model and the second prediction model may include an encoder module, a reconstruction module, and a prediction module which are connected to form two paths, an encoder-reconstruction path and an encoder-prediction path, to preserve more information of historic traffic data.

Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a chamber comprising a support, the support configured to have mounted thereon a substrate; at least one channel disposed in the chamber and into which a conductive fluid or a non-conductive fluid is configured to be injected; and a control unit. The control unit includes a first pump and a second pump configured to respectively supply the conductive fluid and the non-conductive fluid to the at least one channel; and a first valve configured to receive the conductive fluid and the non-conductive fluid from the first pump and the second pump, respectively, and control proportions at which the conductive fluid and the non-conductive fluid are injected into the at least one channel.

Abstract: A memory device and a method for programming the same may include, applying program loops to a plurality of memory cells of the memory device to adjust threshold voltages of the plurality of memory cells to desired target states, each of the program loops including a program section and a verification section, programming the memory cells of a first page, storing a number of first program loops used to complete the programming of the memory cells of the first page to a first target state, programming the memory cells of a second page to the first target state, the second page adjacent to the first page, and performing a verification operation on the second page.