Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.

Abstract: Implementations for providing a mobility management with optimized paging system in a wireless communication system comprising a core network (CN) node and a user equipment (UE) in operative communication with one another through a base station are disclosed. The paging system may, by way of example, be provided in three stages. The first stage is determining whether the destination base station is the same as the source base station, resulting in either first paging if they are the same or to subjecting the base stations belonging to the tracking area list where the UE is found to filtering if they are not the same. The second paging takes place if the destination base station is present in a list of predicted base stations that come as a result of the filtered base stations. The third paging may take place if the destination base stations is not present in the list of predicted base stations.

Abstract: Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. In the semiconductor device, a supporting pattern may be used to fix upper portions of active patterns, when a gap-filling process is performed to fill a region between active patterns, and thus, it may be possible to prevent or reduce the likelihood of the active patterns from being bent or fallen. Thus, it may be possible to reduce failure of the semiconductor device and/or to improve reliability of the semiconductor device.

Abstract: An electronic device includes a circuit board, a socket on the circuit board and electrically connected to the circuit board, and a tray removably insertable into the socket from outside the electronic device, the tray including a body portion, a first protrusion extended from the body portion, and a second protrusion extended from the body and spaced apart from the first protrusion. The socket includes a detection portion which is engageable with the first protrusion of the tray and detects insertion of the tray in the socket, together with the circuit board, and a supporting portion which is engageable with the second protrusion of the tray. The tray which is inserted into the socket disposes the first protrusion contacting the detection portion, and a portion of the tray corresponding to the second protrusion supported by the supporting portion.

Abstract: Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits, and a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads. The cell array structure may include a resistor pattern positioned at the same level as the semiconductor layer, a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer, and vertical structures penetrating the stack.

Abstract: A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.

Abstract: A semiconductor memory device includes a peripheral circuit structure; and a cell structure including a cell substrate and a gate electrode, on the peripheral circuit structure. The peripheral circuit structure includes a peripheral circuit board including a first surface facing the cell structure and a second surface opposite to the first surface, a first circuit element on the first surface of the peripheral circuit board, a first wiring line electrically connected to the first circuit element in a first interlayer insulating layer, a capacitor dielectric layer covering the second surface of the peripheral circuit board, a first capacitor electrode in the capacitor dielectric layer, a second capacitor electrode spaced apart from the first capacitor electrode in the capacitor dielectric layer, and a first connection via electrically connecting the first capacitor electrode with the first wiring line by passing through the peripheral circuit board.

Abstract: A display module may include a substrate and an inorganic light emitting diode on the substrate. The inorganic light emitting diode includes: an active layer configured to generate light having a first color; a light emitting surface spaced apart from the active layer; a groove part including grooves recessed in the light emitting surface; and a quantum dot (QD) layer in the groove part and configured to convert the light having the first color generated in the active layer into a second color. The display module may further include a color filter corresponding to the inorganic light emitting diode and configured to absorb the light having the first color emitted from the inorganic light emitting diode.

Abstract: A speaker module includes a speaker housing including a first speaker housing defining at least one first surface of the speaker module and a second speaker housing defining at least one second surface of the speaker module that is opposite to the least one first surface, a speaker assembly including a voice coil and a vibration member, the speaker assembly being accommodated in an interior of the speaker housing, a back volume in an interior of the speaker housing and defined by the first speaker housing and the second speaker housing, and a side surface shield member between an inner surface of the speaker assembly and the back volume, the side surface shield member including a ferrite-based magnetic substance, where at least one vent hole communicating the speaker assembly and the back volume is in the side surface shield member.

Abstract: An electronic device includes: one or more processors; and memory storing instructions that, when executed by the one or more processors, cause the electronic device to: measure a surface temperature of the electronic device; monitor a load of hardware and an occurrence of preset events; determine a proportional-integral-differential (PID) level of the electronic device based on the surface temperature; set each of a first minimum clock of a first limit clock of a central processing unit (CPU) and a second minimum clock of a second limit clock of a graphics processing unit (GPU), based on the PID level and the load; and determine, such that the surface temperature converges to a first target temperature corresponding to the PID level, the first limit clock to be greater than or equal to the first minimum clock and the second limit clock to be greater than or equal to the second minimum clock.

Abstract: An hinge module configured to pivotably couple first and second housings, includes a hinge bracket, a first rotation member coupled with the first housing and disposed on the hinge bracket pivotably or rotatably around a first folding axis, a second rotation member coupled with the second housing and disposed on the hinge bracket pivotably or rotatably around a second folding axis, a cam member on the hinge bracket to be linearly movable, and an elastic member providing elastic force to the cam member in a direction in which the first rotation member and the second rotation member are brought into close contact. The cam member is configured to press at least part of the first rotation member in a direction crossing the first folding axis or at least part of the second rotation member in a direction crossing the second folding axis based on elastic force of the elastic member.

Abstract: A semiconductor device includes bit lines, which are apart from each other in a first direction and extend in a second direction that crosses the first direction, above a top surface of a substrate, comb-type insulating patterns arranged among the bit lines in the first direction and apart from each other in the second direction, line insulating layers apart from each other in the first direction, extending in the second direction, and covering the bit lines and portions of the comb-type insulating patterns from below, and a conductive line shield layer covering the line insulating layers and the other portions of the comb-type insulating patterns from below.

Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first vertical channel pattern and a second vertical channel pattern on the bit line, a back gate electrode between the first vertical channel pattern and the second vertical channel pattern and extending in a second direction perpendicular to the first direction across the bit line, a first word line extending in the second direction from one side of the first vertical channel pattern, a second word line extending in the second direction from other side of the second vertical channel pattern, and a contact pattern connected to each of the first vertical channel pattern and the second vertical channel pattern. When viewed from a cross-sectional view, each of the first vertical channel pattern and the second vertical channel pattern have a trapezoidal shape with the long sides facing each other.

Abstract: A method of training a physical interface between a first device and a second device includes performing a first training of the physical interface by communicating with the second device by using a first candidate group of lanes from among a plurality of lanes; performing a second training of the physical interface by communicating with the second device by using a second candidate group of lanes from among the plurality of lanes, the second candidate group being different from the first candidate group; determining a lane group based on a result of the first training and a result of the second training; and setting the second device so that the determined lane group is used for the physical interface.

Abstract: Provided is a semiconductor device which includes: 1st source/drain regions connected through a 1st channel structure which is controlled by a 1st gate structure; and a 2nd source/drain regions, respectively above the 1st source/drain regions, connected through a 2nd channel structure which is controlled by a 2nd gate structure, wherein the 1st channel structure and the 2nd channel structure comprise different materials.

Abstract: A storage device includes a storage controller and a non-volatile memory including a first memory region including first memory cells having a first data retention time and a second memory region including second memory cells having a second data retention time that is shorter than the first data retention time. Based on an erase request being received from a host in a first operation mode, the storage controller determines whether to switch from the first operation mode to a second operation mode. The storage controller programs program data in a memory region selected from the first memory region and the second memory region in the first operation mode, and the storage controller programs the program data in only the first memory region in the second operation mode.

Abstract: A storage device includes a plurality of memory dies, corresponding to a plurality of channels and a plurality of ways, and a storage controller connected to the plurality of memory dies. The storage controller may be configured to receive commands from a plurality of tenants; in response to a number of the received commands being equal to or greater than a predetermined threshold value, determine a first number of channels required to store first data of a first tenant in each way of the plurality of ways based on commands received from the first tenant; and store the first data in the first number of memory dies in each way of the plurality of ways. The first data may be stored in memory dies that correspond to the plurality of channels in at least a portion or an entire portion of the plurality of ways.

Abstract: A storage device includes at least one non-volatile memory device, and processing circuitry configured to control the non-volatile memory device and communicate with at least one external host device through at least one interface channel, wherein the processing circuitry is further configured to, monitor performances of a plurality of virtual functions, generate status information of the plurality of virtual functions based on the monitored performances of the plurality of virtual functions, and allocate one or more resources to the plurality of virtual functions in real time based on the status information associated with the respective virtual function of the plurality of virtual functions.

Abstract: A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.