Abstract: A cooking apparatus includes a housing, a heat source on one side of the housing, a control panel couplable to the housing, a knob rotatably mountable on the control panel to operate the heat source and movable rearwardly, a stopper between the control panel and the knob and including an anti-rotation portion configured to prevent a rotation of the knob, a button movably couplable to the knob in a left-to-right direction, and a locking pin accommodated in the anti-rotation portion and secured to the button so as to move along the button. The locking pin is deviated from the anti-rotation portion based on movement of the button, the knob is rotatable while the knob is moved rearwardly and the locking pin is deviated from the anti-rotation portion, and the knob is rotated to operate the heat source.

Abstract: A home port includes: a cylindrical body including: an open upper, a lower end, and an outlet in the lower end of the cylindrical body; a cover covering the open upper end; a pipe connected to the outlet; and a first bracket between the cover and the outlet, wherein a hole is provided in the first bracket, the first bracket has an inclined surface inclined from a first side of the first bracket to a second side of the first bracket, a vertical level of the first side of the first bracket is higher than a vertical level of the second side of the first bracket, and the hole of the first bracket is provided at the second side of the first bracket.

Abstract: A method includes performing a substrate processing process by carrying a substrate into a chamber, and disposing the substrate in a loading region of the chamber, capturing an image of a lower surface of the substrate to acquire a first image, identifying particle patterns formed on the lower surface of the substrate in the substrate processing process, and an edge of the substrate, from the first image, calculating a first alignment error value of a deviation between an approximate position value for the center of the loading region calculated from the particle patterns and an approximate position value for a center of the substrate calculated from the edge of the substrate, and determining a point in time for teaching a transfer robot that deposits the substrate into the chamber, based on the first alignment error value.

Abstract: A clothes treating system may include a washing machine including a tub; a dryer including a heat pump and a fan; a first flow path; a damper to open and close the first flow path; a second flow path; a humidity sensor to detect humidity inside the tub; and a controller configured to: determine whether to perform a tub drying cycle, based on the detected humidity, and based on determining to perform the tub drying cycle, open the first flow path with the damper, operate the heat pump to heat air, and operate the fan to move the heated air through the first flow path, so that air flows into the tub through the first flow path and moisture from the tub is absorbed by the air and flows into the dryer through the second flow path.

Abstract: A chalcogenide-based memory material may include a ternary semiconductor compound having a composition represented by XaY?bSec, wherein the chalcogenide-based memory material may have an ovonic threshold-switching (OTS) characteristic, and a threshold voltage of the chalcogenide-based memory material may change according to a polarity and an intensity of an applied voltage. In XaY?bSec, X?Y, a+b+c=1, a>0.12, b>0.18, c?0.4, and X and Y? independently may be different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P. A memory device may include the chalcogenide-based memory material. An electronic apparatus may include the memory device.

Abstract: An image sensor may include photoelectric conversion elements within a substrate, a separation structure within the substrate and between the photoelectric conversion elements, an insulating structure on the substrate and the separation structure, a plurality of color filters on the insulating structure, a grid structure including a lower horizontal structure disposed on the insulating structure and a vertical structure connected to the lower horizontal structure and covering a side surface of one of the plurality of color filters, upper horizontal structures covering upper surfaces of the plurality of color filters, and a capping layer covering the upper horizontal structures and the grid structure. The grid structure may further include an air gap surrounded by the vertical structure, the lower horizontal structure, and the capping layer.

Abstract: A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a substrate; a chip spaced from the substrate and having a first surface, a second surface and a side surface, the first surface of the chip including a photosensitive area and a non-photosensitive area surrounding the photosensitive area; a molding layer having a first surface and a second surface, the molding layer provided on the non-photosensitive area of the chip and the side surface of the chip.

Abstract: An image sensor includes a substrate including a first surface and a second surface which is opposite to the first portion, and a pixel isolation portion provided in the substrate and configured to isolate unit pixels from each other. The pixel isolation portion includes a first filling insulation pattern extending from the first surface toward the second surface and having an air gap region, the first filling insulation pattern including a first sidewall and a second sidewall which is opposite to the first sidewall, a conductive structure including a first portion on the first sidewall, a second portion on the second sidewall, and a connection portion connecting the first portion and the second portion, and an insulating liner provided between the first portion and the substrate and between the second portion and the substrate.

Abstract: The present disclosure provides a high electron mobility transistor including a channel layer; a barrier layer on the channel layer and configured to induce formation of a 2-dimensional electron gas (2DEG) to the channel layer; a p-type semiconductor layer on the barrier layer; a first passivation layer on the barrier layer and including a quaternary material of Al, Ga, O, and N; a gate electrode on the p-type semiconductor layer; and a source electrode and a drain electrode provided on both sides of the barrier layer and separated from the gate electrode.

Abstract: An integrated circuit device includes a substrate having formed therein a word line trench extending long in a first horizontal direction, a gate dielectric film covering an inner surface of the word line trench, a word line on the gate dielectric film, the word line filling a lower space of the word line trench and extending long in the first horizontal direction, an insulating capping pattern on the word line, the insulating capping pattern filling an upper space of the word line trench and extending long in the first horizontal direction, and at least one ferroelectric layer arranged at a top portion of the word line and including a first sidewall in contact with the gate dielectric film.

Abstract: A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.

Abstract: A memory device includes: a channel layer; a gate electrode spaced apart from the channel layer; and a multilayer charge trap layer disposed between the channel layer and the gate electrode, wherein the multilayer charge trap layer includes silicon oxynitride, the silicon oxynitride including gallium or silicon nitride including gallium.

Abstract: A semiconductor package includes a first semiconductor chip having first and second surfaces opposing each other; first lower electrode pads on the first surface; a first insulating layer surrounding a side surface of each of the first lower electrode pads on the first surface; through-electrodes penetrating through at least a portion of the first semiconductor chip; first upper electrode pads on the through-electrodes; a first dielectric layer covering at least a portion of each of the first insulating layer, the first semiconductor chip, the through-electrodes, and the first upper electrode pads on the through-electrodes; where the first dielectric layer comprises a first portion and a second portion on the first portion of the first dielectric layer, and a first outer surface of the first portion is located on an inner side closer to the first semiconductor chip than a second outer surface of the second portion.

Abstract: A semiconductor package including: a base structure including upper and lower surfaces with upper and lower connection pads, the upper connection pad being connected to the lower connection pad; a plurality of first semiconductor chips stacked on the base structure, wherein the plurality of first semiconductor chips includes uppermost and lowermost chips, and wherein each of the plurality of first semiconductor chips includes a first lower and upper pads, and a silicon via connecting the first lower and upper pads; a cover chip, on the uppermost semiconductor chip, including an upper surface with a flat region and an edge region; and an upper dummy chip on the flat region and including an area smaller than an area of the cover chip and a thickness greater than a thickness of the cover chip, wherein the first lower pad of the lowermost chip is connected to the upper connection pad, and wherein the first upper pad of each of the plurality of first semiconductor chips, except for the uppermost chip, is connected

Abstract: According to an embodiment of the disclosure, an electronic device may comprise a first housing, a second housing configured to provide a motion relative to the first housing, a flexible display configured to transform in response to the motion of the second housing relative to the first housing, and a display protection layer disposed on one surface of the flexible display facing in a first direction. The display protection layer may include a glass layer including a first flat area having a first thickness and disposed on the first housing, a second flat area disposed on the second housing, and a folding area connecting the first flat area and the second flat area, and a coating layer disposed between the glass layer and the flexible display. The folding area of the glass layer may include a first area having a second thickness different from the first thickness and a second area connecting the first area and the flat area and having a third thickness smaller than the second thickness.

Abstract: A memory device includes: memory operation circuitries to perform memory processing; memory banks assigned to one of the memory operation circuitries such that a set of n memory banks is assigned to each of the memory operation circuitries; and command pads to receive a command signal from an external source, wherein, for each of the memory operation circuitries, a corresponding memory operation circuitry to access memory banks of a corresponding set of n memory banks that is assigned to the corresponding memory operation circuitry, in an order determined based on respective distances from each of the memory banks of the corresponding set of n memory banks to the command pads, and wherein, each of the memory banks of the corresponding set of n memory banks to perform an access operation of data requested by the corresponding memory operation circuitry while the memory processing is performed.

Abstract: A method and a device for managing a tab window indicating a group including heterogeneous applications. The method includes outputting a display window comprising at least one or more objects for executing one or more applications on a terminal window, receiving a user input that selects the at least one or more objects and moves the selected at least one or more objects to a region excluding the display window, generating an application group comprising at least one or more applications corresponding to the selected at least one or more objects according to the received user input, and outputting a tab window indicating the generated application group to the terminal window.

Abstract: A method for performing multi-token prediction by an apparatus includes receiving, from an artificial intelligence (AI) assistance device, a request for an output token sequence that is subsequent to an input token sequence indicated by the request, predicting, by a trained machine learning model, a plurality of candidate output tokens, estimating joint probability distributions of one or more combinations of the plurality of candidate output tokens, calculating joint probabilities of the one or more combinations by masking the joint probability distributions with a co-occurrence weighted mask, determining, based on the joint probabilities, whether to reduce the number of candidate output tokens included in each combination of the one or more combinations, identifying, based on the joint probabilities, a combination of the one or more combinations as the output token sequence, and outputting, to the AI assistance device, a response to the request, the response comprising the output token sequence.

Abstract: A method includes receiving data from one or more sensors, detecting, from the received data, one or more activities of a person in a space, converting the detected one or more activities into a natural language narration; extracting one or more items from a map corresponding to the space; determining a relevancy score for each of the extracted one or more items based on an output of a language model that receives as input a combination of the narration with a binding sequence; correlating the extracted one or more items with one or more locations on the map based on the determined relevancy for each of the extracted one or more items; and outputting a control signal for controlling a movement of one more devices based on the correlation of the extracted one or more items with the one or more locations on the map.

Abstract: A method and apparatus for training a neural network model are provided. The method of training a neural network model includes storing replay samples selected from among online stream samples in a replay buffer, selecting batch samples from the replay samples based on selection frequencies of the respective replay samples, determining a freeze layer group of the neural network model based on forward propagation of the neural network model using the batch samples, and training the neural network model based on backward propagation of layers not in the freeze layer group.