Abstract: An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite the first surface; a rail through via passing between the first surface and the second surface of the substrate; a cell-level portion arranged on the first surface and comprising a buried rail connected to the rail through via, a local conductive interconnect, a cell via connected to the local conductive interconnect, and a transistor connected to the local conductive interconnect; a signal wiring-level portion arranged on the cell-level portion and comprising a plurality of upper multi-layer interconnect layers connected to the local conductive interconnect via the cell via and upper vias connecting the upper multi-layer interconnect layers to each other; a dummy substrate arranged on the signal wiring-level portion; a bonding-level portion arranged between the signal wiring-level portion and the dummy substrate and bonding the signal wiring-level portion to the dummy substrate, and comprising

Abstract: The present disclosure relates to a method and apparatus for performing communication in a wireless communication system. A user equipment (UE) may receive, from a base station, at least one of secondary cell (SCell) configuration information, channel state measurement configuration information, and timer configuration information used for discontinuous reception (DRX), measure a channel state based on the received configuration information, and transmit information about the measured channel state to the base station.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

Abstract: Provided is an image decoding method including determining a plurality of coding units in a chroma image by hierarchically splitting the chroma image, based on a split shape mode of blocks in the chroma image of a current image, and decoding the current image, based on the plurality of coding units in the chroma image. In this regard, the determining of the plurality of coding units in the chroma image may include, when a size or an area of a chroma block from among a plurality of chroma blocks to be generated by splitting a current chroma block in the chroma image is equal to or smaller than a preset size or a preset area, not allowing splitting of the current chroma block based on a split shape mode of the current chroma block, and determining at least one coding unit included in the current chroma block.

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

Abstract: Embodiments of the present disclosure provide methods and apparatuses for facilitating restricted target wake time (TWT) operation in a wireless local area network. The apparatuses include a non-access point (AP) multi-link device (MLD) comprising a plurality of stations (STAs) and a processor. Each STA comprises a transceiver configured for broadcast TWT operation on multi-link operation (MLO) links with corresponding APs of an AP MLD. The processor is operably coupled to the transceivers, and configured to negotiate a broadcast TWT schedule over a first link between a first STA and a first AP of the AP MLD, apply the broadcast TWT schedule to the group of links, negotiate a restricted TWT schedule with the AP MLD over at least one link of the group of links, and establish the restricted TWT schedule on one or more links of the at least one link.

Abstract: A memory device includes; a memory cell array including a first memory cell region and a second memory cell region, a voltage generator configured to generate a code corresponding to a write voltage, and a write driver configured to store data in the first memory cell region in response to the code. The second memory cell region stores a value defining the write voltage, and the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.

Abstract: A memory device includes a substrate and a stack including word lines and interlayer insulating patterns alternatingly stacked on the substrate. The word lines extend in a first direction. Semiconductor patterns cross the word lines and have longitudinal axes parallel to a second direction. The semiconductor patterns are spaced apart from each other in the first direction and a third direction. Bit lines extend in the third direction and are spaced apart from each other in the first direction. Each of the bit lines contacts first side surfaces of the semiconductor patterns spaced apart from each other in the third direction. Data storage elements, which are respectively provided between vertically adjacent interlayer insulating patterns and contact second side surfaces opposite to the first side surfaces, and substrate impurity layers provided in portions of the substrate at both sides of the stack, are included.

Abstract: A semiconductor memory device includes a first power supply unit configured to, in a normal mode of a high frequency operation, supply a first power from a first global power rail to a third global power rail and a fourth global power rail in a normal mode, and, in a standby mode of a high frequency option, supply the first power to the third global power rail and not supply the first power to the fourth global power rail, and, in a normal mode of a low frequency operation, supply a second power of a second global power rail to the third global power rail and the fourth global power rail, and, in a standby mode of a low frequency operation, supply the second power to the third global power rail and not supply the second power to the fourth global power rail.

Abstract: A method performed by a first terminal is provided. The method includes determining whether a first delay related to the first terminal is necessary, transmitting, to a second terminal, a delay message including first delay information in case that the first delay is necessary, in response to the delay message, receiving, from the second terminal, an allocation message including information on one or more nodes, determining whether information on the first terminal is included in the information on one or more nodes included in the allocation message, and allocating the first delay in case that the information on the first terminal is included in the information on one or more nodes.

Abstract: An electronic device is disclosed. The electronic device comprises: a transfer device capable of moving, to a target substrate, a plurality of LEDs arranged in a transfer substrate, and arranging same; a storage unit in which feature information of each of the plurality of LEDs is stored; and a processor for controlling the transfer device such that each of a plurality of LEDs is arranged in an arrangement location on the target substrate of each of a plurality of LEDs on the basis of the stored feature information.

Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method includes configuring, by a User Equipment (UE) (100), a Protocol Data Unit (PDU) session type as an always-ON type or a normal PDU type. Further, the method includes sending, by the UE (100), a PDU session establishment request message including the PDU session type to be the always-ON type or the normal PDU type to a network (200) during an initial PDU session establishment procedure.

Abstract: A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.

Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines.

Abstract: A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.

Abstract: An organic light-emitting device which including a first electrode, a second electrode facing the first electrode, and an emission layer disposed between the first electrode and the second electrode, wherein an emission layer includes a first material, a second material, and a third material satisfying certain conditions.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

Abstract: A semiconductor memory device may include at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in the first direction, at least one gate electrode on the horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction, and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, wherein a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor device on an active surface thereof. The semiconductor substrate has a quadrangular plane. An insulating layer is on the active surface of the semiconductor substrate. A passivation layer is on the insulating layer. The insulating layer includes an insulating layer central portion having a side surface extending in parallel with a side surface of the semiconductor substrate. The side surface of the insulating layer central portion is spaced apart from the side surface of the semiconductor substrate by a first size. An insulating layer corner portion is at each corner of the insulating layer central portion and protrudes from the side surface of the insulating layer central portion in a horizontal direction. The passivation layer covers the insulating layer central portion.

Abstract: A vertical type non-volatile memory device includes a substrate having a cell array area of a block unit and an extension area, a vertical contact disposed in the extension area, a plurality of vertical channel structures provided on the substrate in the cell array area, a plurality of dummy channel structures provided on the substrate in the extension area, and a plurality of gate electrode layers and a plurality of interlayer insulation layers stacked alternately on the substrate. In an electrode pad connected to the vertical contact, dummy channel structures are disposed at both sides of the vertical contact and a horizontal cross-sectional surface of each of the plurality of dummy channel structures has a shape which is longer in one direction.