Abstract: A start-up circuit for a bias generating circuit includes a current source for providing a small charging current, and transistors for coupling the charging current to the bias generating circuit during power up to force the bias generating circuit into a steady-current state. The start-up circuit also uncouples the current source from the bias circuit after the bias generating circuit is forced into the steady-current state to prevent the charging current from affecting the operation of the bias generating circuit.

Abstract: An improved crystal oscillator and output circuit is disclosed. The oscillator has a normal operating mode and a low-power mode. In the low-power mode, a reduced current which is sufficient to maintain oscillation is supplied to the oscillator and the output circuit is disabled. The oscillator can subsequently be returned to normal mode and the output circuit enabled. Since the oscillator is never shut completely off, the time required to resume normal mode oscillations is reduced.

Abstract: A programmable output driver circuit is provided having multiple drive capabilities for optimizing noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.

Abstract: A high-frequency voltage controlled oscillator includes a start-up circuit for preventing the oscillator from enering a stable state and that does not increase the fixed delays in the oscillator feedback paths. A sleep mode feature shuts down the oscillator to conserve power and capacitors are used to isolate the oscillator from high-frequency noise coupled through the power supply inputs.

Abstract: In a CMOS bandgap reference circuit, the respective collectors of two lateral parasitic NPN transistors are connected to the two nodes of a current mirror. The emitter circuit of the first parasitic NPN transistor includes a resistor, whereby the base-emitter junction current densities of the parasitic NPN transistors are maintained at a preselected ratio. A second resistor common to the emitter circuit of both parasitic NPN transistors is provided, whereby .DELTA.V.sub.BE having a positive temperature coefficient and V.sub.BE of the second parasitic NPN transistor having a negative temperature coefficient cancel one another. The temperature independent voltage across the common resistor and the base-emitter junction of the second transistor is buffered by a unity gain amplifier. The output of the unity gain amplifier is used to drive the parasitic NPN transistors and also is furnished as the reference voltage.

Abstract: This invention provides a method for manufacturing a semiconductor device which prevents residues from remaining around an etching pattern of a poly-silicon by making the poly-silicon be gradiently etched out. An oxide barrier layer is deposited over a poly-silicon layer, and impurities are implanted through the oxide barrier layer, wherein the concentration difference of impurities makes the poly-silicon have a graded sidewalls, and the value of resistance is controlled by the quantity of impurities. After removing the oxide barrier layer the poly-silicon is selectively etched into a poly electrode having a graded sidewall. The thermal treatment of the poly electrode is carried out and a polysilicon for another electrode is deposited and etched out.

Abstract: For a SRAM having a sense amplifier amplifying memory data and a read/write control circuit controlling operations of the sense amplifier, a data output buffer circuit is provided, which includes: a drive output node from which data output buffer provides output data; a first circuit providing a NOR function of an SAS signal from the sense amplifier and an output enable signal (OE) from the read/write control circuit; a second circuit providing a NOR function of an SAS signal from the sense amplifier and the output enable signal (OE) from the read/write control circuit; a third circuit eliminating noise produced by transition in the outputs of the first and second circuit and also enhancing a response time; a fourth circuit inverting the output of the first circuit; a fifth circuit inverting twice, sequentially, the output of the second circuit; and a sixth circuit responsive to the fourth and fifth circuit, alternatively providing, depending on the SAS and an SAS signal from the sense amplifier, one of three

Abstract: A laser fuse signature circuit for testing whether a fuse link in an IC has been disconnected includes a first series circuit connecting the power and ground pins and a second series circuit, including the fuse and a plurality of diode devices, connecting an input pin to a first node in the first series circuit. Transistors included in the first series circuit are connected so that the laser fuse signature circuit does not conduct current during normal operation or leakage current testing of the IC.

Abstract: A power-on reset circuit. The reset circuit provides an automatic reset pulse immediately after power-up. The supply voltage is provided to the reset circuit. An RC filter with a variable time constant provides a "hump" waveform which is coupled to a waveform shaper. The waveform shaper converts the hump voltage output from the RC filter into a reset signal. Latching mechanisms are included to prevent refiring of the reset signal.

Abstract: The present invention relates to a level translator which translates TTL level signals to ECL level. The translating speed is enhanced by making the input circuit of the level translator which receives the TTL data signal composed of an emitter coupled pair such that the circuit does not act in saturation mode. Also, by designing the circuit to make current flow from the pull-up transistor of the TTL transfer through the resistance of the present invention when the TTL data is high level, and to make current flow through the pull-down transistor of the driving TTL circuit into the TTL to ECL level translator when low level, the present invention makes the time delay from the driving TTL circuit to the ECL receiving circuit very small.

Abstract: This invention is related to a semiconductor light emitting device integrated with a Si-heat sink which contains not only a beam deflector but also the driving integrated circuits. A semiconductor light emitting device comprising a Si-substrate 2, V-groove 3 etched into substrate 2 and a beam deflector 9 on the wall of V-groove 3 wherein the transistor 22 for the driving and control on said Si-substrate is integrated so that light emitting device 1 and said integrated circuit are integrally mounted. The advantage of this invention is that the integration of the driving transistor with the light emitting device in the same package head reduces the packaging and bonding problems. Obtained is a compact optical system which easily radiates the heat dissipated by devices. This is in contrast to conventional light emitting devices which use the Si-substrate only as a mount and beam deflector.

Abstract: This invention is related to a method for fabricating a DRAM cell. This invention makes the capacitor electrode and the source of the transistor connect more easily using the lateral diffusion of another dopant having higher diffusivity and same impurity type, which is added to the first ion implantation for the first electrode of storage capacitor. According to this invention the storage capacitor electrode and the source of the transistor are connected successfully, and it is possible to reduce the resistance between the capacitor electrode and the drain of the transistor.

Abstract: The present invention uses two pairs of cross coupled n-channel sense amplifier transistors attached between two electrically balanced halves of a bit line. Disposed between each pair of cross coupled n-channel sense amplifier transistors is only one pair of p-channel restore transistors attached between the bit line and complement bit line. Furthermore, on the bit line and complement bit line, between one pair of cross coupled n-channel sense amplifier transistors and the pair of p-channel restore transistors, are depletion type isolating transistors that further isolate halves of the bit line and complement bit line.

Abstract: Present invention relates to the fabrication method of the bipolar transistor which includes NPN transistor and field-plate lateral PNP transistor.The arsenic implanted polycrystalline silicon is used for the emitter electrode of NPN transistor to increase the current gain, and for the field-plate of the lateral PNP transistor to reduce the collector-emitter leakage current.Also, this polycrystalline silicon is used for the ion implanting mask for the extrinsic base of the NPN transistor and for the emitter, collector of the lateral PNP transistor simultaneously.Therefore, the extrinisc base of NPN transistor and the emitter, collector of the lateral PNP transistor are self-aligned by the polycrystalline silicon, and so one mask is saved by this method.

Abstract: A multiplexing parallel analog digital converter including two multiplexers, comparators, a demultiplexer, and a control unit. One multiplexer is provided the reference voltages resulting from a voltage division of inner resistors by a most significant bit reference ladder and a least significant bit reference ladder for the reference voltage of the next comparison. The other multiplexer is provided the reference voltages by accepting an analog input signal and the difference signal between an analog input signal and the output of a 4-bit digital analog converter. By using two multiplexers, only one analog digital converter is needed in this present device, so, the number of comparators is reduced. The multiplexer sends the digital signals compared with the most significant bit signal and the least significant bit signal, respectively, to a most significant output latch and a least significant output latch, respectively, so the 8-bit digital signal is obtained.

Abstract: A precharge system of the divided bit line types for a SRAM (Static Random Access Memory) reduces the active current consumption and bit line peak current by decreasing the number of bit lines to be precharged at any one time during a precharge cycle. For this, the system has a block selection signal generator that responds to certain column addresses with a block selection signal. A sub-block selection signal generator responds to certain addresses among the remaining column addresses with a sub-block selection signal. A precharge decoder responds to pulses from the pulse generator and the block selection signal with a block selection precharge signal. A divided bit line precharge decoder responds to the sub-block selection signal and block selection precharge signal with a pulse for precharging only a certain sub-block of a certain block of the array of memory cells of the SRAM.

Abstract: The present invention implements a static inverter-type TTL/CMOS level translator. The present invention utilizes a pair of transistors to suppress hot electron effects. The transistor pair limits maximum VDS to VCC-VTN at the first and second gain stages. A pair of resistors serve as a virtual VCC modulator to minimize voltage variations, stabilizing the VIL/VIH trip point. The resistors also minimize standby current so that the translator of the present invention can be used in a low standby current environment. The translator of the present invention provides faster speed, wider process margins, better reliability and lower standby current than prior art translators.

Abstract: A TTL to CMOS buffer circuit includes a first buffer receiving a TTL input and a second buffer providing a CMOS output. The first buffer has a first power input connected to Vcc, a second power input connected through a resistor to Vcc, and a third power input connected to Vss. The second buffer has a first power input connected to Vcc, a second power input connected through a resistor to Vss, and a third power input connected to Vss. In the first buffer, two PMOS transistors and three NMOS transistors are serially connected by their current electrodes between the second and the third power input, in that sequence; the second power input is connected to the P channel transistor end of the series and the third power input is connected to the N channel end of the series.

Abstract: A junction-breakdown protection semiconductor device provides a well region which prevents the junction between a metal conductor and a diffused region from breakdown even under a high voltage or high current input. The junction-breakdown protection semiconductor device includes a metal conductor to which a high voltage is applied a semiconductor region of high impurity concentration having a conductivity type which is opposite to the conductivity type of the substrate is connected to the metal conductor through an opening in an insulating film. A second semiconductor region of the same conductivity type as the first semiconductor region is formed deeper in junction depth than the first semiconductor region under the opening in the insulator for ohmic connection on the surface of the first semiconductor region.

Abstract: A dual-slope waveform generation circuit without a DC path and with decreased layout area including a pull-up and pull-down resistor, a transmission gate and an inverter. An input signal IN is applied to the pull-up transistor, to each gates of MOS transistors M.sub.1, M.sub.2 composing of the inverter A, and to drains of MOS transistors M.sub.3, M.sub.4 composing of the transmission gate B. A common node in the inverter is connected to the gate of the N type MOS transistor in the transmission gate. The sources of the transistors M.sub.3, M.sub.4 are connected to the gate of the pull-down transistor. An output signal OUT is applied to the gate of the transistor M.sub.4 and the signal is fed back.