Abstract: A FM detection system using a phase locked loop (PPL 20) and including: a wave shaping comparator (7) for accepting a signal V.sub.CO2 from a voltage controlled oscillator (4) which is 90.degree. out of phase with a control signal V.sub.CO1 from the voltage controlled oscillator (4), the comparator reshaping the signal to a square wave; an in-lock detector (8) for accepting the square wave and a frequency modulated input signal (VFM) to provide a sum frequency and a difference frequency; a low-pass filter (9) cutting off the sum frequency component, and filtering out the difference frequency signal when the PLL (20) is unlocked; a comparator (10) for comparing the output of the low-pass filter (9) with a reference voltage (V.sub.

Abstract: Present invention relates to the fabrication method of the bipolar transistor.With this method the emitter of high-concentrated n-type is contacted closely to the extrinsic base of high-concentrated p-type.This structure is obtained by making the emitter of the bipolar transistor be self- aligned by the side wall under-cut of the nitride layer using double layers of the low temperature oxide and the nitride layer.

Abstract: A level shifter for an input/output bus in a CMOS dynamic RAM employs a first and second PMOS transistor. The first and second PMOS transistors are connected to and cut off a current flow between a pair of input/output lines and a pair of input/output sense amplifier input lines which are connected to input/output sense amplifiers. First and second inverters are included for each of the first and second PMOS transistors, each inverter has an input for receiving a signal for a selection of the input/output line pair and has a respective output which is connected to a corresponding gate and drain of the first and second PMOS transistors.

Abstract: A sense amplifier and high performance DRAM, in combination, has in the DRAM at least one row of memory cells, whereby the memory cells of the row may be arranged in respective columns with memory cells of other rows. Each of the memory cells has a transistor and a capacitor connected serially between one of bit lines successively along the row and a fixed voltage source. Word lines are respectively connected to gates of the transistors of the memory cells for activating the memory cell selectively according to row address. The sense amplifier has a cross-coupled bistable flip-flop connecting the bit lines to each other in the row. A latch transistor connected to the flip-flop detects and amplifies a voltage difference between the bit lines. The bit lines are equalized and precharged with a reference voltage in response to a clock control signal. A cross-coupled pair of transistors also connecting the bit lines to each other transfer a charging voltage to the bit lines.

Abstract: This invention is related to an integrated driving circuit which can control high voltage and power, and more particularly to a high voltage and power driving circuit by employing BiCMOS technology. The principal object of this invention is to provide an integrated high voltage and high power driving circuit which is reliable by using BiCMOS technology without external discrete components.

Abstract: This invention provides a method for fabricating a BiCMOS device, in which said device has a Si substrate of a first conductivity in which there is formed a first substrate region of a second conductivity for a bipolar transistor, a second substrate region of said second conductivity for a first MOSFET, having a source and drain of the first conductivity, and in which a part of said Si substrate is formed to provide a second MOSFET which has a source and drain of the second conductivity. A first nitride layer is used to prevent the substrate under a masking layer from oxidizing during the following oxidation processes, wherein the masking layer is composed of a oxide layer and the nitride layer. After some processes, the masking layer is removed. Implanting As impurities, a new oxide layer and a new nitride layer are deposited, wherein the role of the nitride layer is to protect a shallow emitter region.

Abstract: A C-MOS address buffer for use in a semiconductor memory device is clocked by an inverted column address strobe signal .phi..sub.CAL of an external column address strobe signal CAS. The signal .phi..sub.CAL is supplied to the drain of a feedback transistor in a schmitt trigger and is reinverted to provide a signal corresponding to the address strobe signal CAS. This signal is coupled to the gate of a transistor which controls the application of a supply voltage to the schmitt trigger circuit. Invalid timing address signals between the address input signal Ai and the clock signal comprising the signal .phi..sub.CAL are thus prevented. Also sufficient address set up time and hold time are guaranteed.

Abstract: A sense amplifier having an optimized structural lay-out for D-RAM on the C-MOS provides the same time lag from nodes of the sense amplifier and does not produce unbalances in the voltages. This allows the sense amplifier to uniformly distribute the parasitic capacitance of the bit lines used for the D-RAM on the C-MOS. The sense amplifier is connected to a memory cell array so that transistors and capacitors are coupled with a plurality of bit lines and word lines situated on the semiconductor substrate. The amplifier has a first semiconductor region which is within an N type well region located on the P type semiconductor substrate to form a first latch circuit. A second semiconductor region which is contiguous to the N type well region is also formed on the semiconductor substrate to form an N-MOS transistor. Lastly, a third semiconductor region, which is contiguous to the N type well region and the second semiconductor region, forms a second latch circuit having an N-MOS transistor.

Abstract: A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are complementary to the input signals of one of the other program devices. The program of the program devices have two steps to repair the faulty cells. To increase the reliability of redundancy, a nonvolatile memory element used in the program devices is a bridge connected four cell FLOTOX type nonvolatile memory device.

Abstract: A data transmission circuit for CMOS dynamic random access memory devices having a data input buffer for converting TTL input data signals to CMOS logic level data signals and providing true and complement data signals on a pair of data bus lines, a pair of transmission gates for transmitting the true and complement data signals to a pair of true and complement I/O bus lines comprising a pair of similar constitutional I/O bus line pull-up or pull-down circuits between the output lines of the transmission gates and the I/O bus lines for making logic operations on the data bus lines. The I/O bus lines alternate at the time of a writing operation and a I/O bus line equalizing circuit is connected between the true and complement I/O bus lines for equalizing the pair of the I/O bus lines at a high speed, before or after a writing cycle.

Abstract: The present invention relates to an integrated circuit for driving a d.c. motor with radio control comprising a receiving circuit for receiving and detecting certain signals transmitted from a transmitter, an amplifier for amplifying an output signal of said receiving circuit, a peak detector for converting the said amplified audio signal into a d.c. voltage, a comparator which have a hysteresis character dependent on the output level of the peak detector, a voltage regulating circuit supplying a stabilized voltage into all other components, and a direction control circuit to generate logic control signals deciding actual operation mode of the d.c. motor and motor driving circuits to produce motor driving signals by the output signal of the direction control circuit.

Abstract: The present invention relates to a linear integrated circuit for driving a d.c. motor with remote radio control comprising an amplifier B.sub.1 to amplify the signal transmitted by the transmitter, a peak detector B.sub.2 detecting the said signal, a comparator B.sub.3 triggered by the d.c. output voltage of the said detector, transistors Q.sub.1 ', Q.sub.2 ' of the driving stage circuit B.sub.4, which can invert the driving direction of the d.c. motor by on or off operation of the said transistors in accordance with the output voltage of the said comparators, a voltage regulator circuit B.sub.5 and a thermal protection circuit B.sub.6 stabilizing the said transistors thermally.