Abstract: An apparatus is provided that includes a NAND string including a first memory cell coupled to a first word line, and a control circuit coupled to the NAND string. The control circuit is configured to apply a verify voltage to the first word line, perform a verify test on the first memory cell to sense a hole conduction current, and perform a program operation on the first memory cell without performing a pre-charge operation.

Abstract: A memory apparatus has memory cells grouped into a first plane and a second plane and are configured to retain a threshold voltage corresponding to data states. A control means applies one of a plurality of program pulses followed by a verify pulse of at least one verify voltage to a group of the memory cells of the first plane and the second plane during one of a plurality of program-verify iterations. The control means terminates programming of one of the first plane or the second plane prior to completing programming of the one of the first plane or the second plane in response to determining the one of first plane or the second plane programs slower. The terminated plane is additionally determined based on sensing the threshold voltage of the memory cells for a long sense time longer than used during the one of the plurality of program-verify iterations.

Abstract: A storage device may maintain persistent data after converting from firmware associated with a first mode to firmware associated with a second mode. The device receives a firmware package associated with the second mode, determines when the package includes a descriptor, and executes a copy macro in the descriptor to translate a first data structure used in the first mode to the second data structure used in the second mode. When the device receives a commit command and determines that the second data structure is in a volatile memory, the device copies the second data structure to a non-volatile memory. After completing the commit command and power cycling, when the device is being formatted in the second mode, the device reads the second data structure from the non-volatile memory, transfers the second data structure to a persistence module, and formats in the second mode.

Abstract: A storage device postpones entry into a read-only mode due to faulty blocks that cannot be written to on a memory device. The memory device is divided into blocks. Blocks used for storing host data are placed in a main area pool, blocks used for storing host data and for peak write operations are placed in a burst pool, and blocks used for storing control information are placed in the control pool. A controller executes a read-only mode extension protocol to determine when a number of faulty blocks in the main area pool, control pool, or burst pool is approaching a threshold for placing the storage device in a read-only mode. If the storage device is approaching the read-only mode, the controller reduces and/or repurposes a number of the blocks used for storing host data in the burst pool to prevent the storage device from entering the read-only mode phase.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

Abstract: A storage device may utilize a host memory buffer for re-ordering commands in a submission queue. Out of order commands in a submission queue that uses host virtual buffers that are not the same size may be difficult to search. Accordingly, commands in a submission queue may be correctly ordered in a host memory buffer before being put into the host virtual buffers. When the commands are in order, the search operation for specific data is improved.

Abstract: A data storage device includes a memory and a controller. The memory includes a first partition and a second partition. The controller includes a pattern detector that is configured to detect one or more tags in data from an access device to be stored in the first partition. The controller is configured to generate, in the second partition, one or more links to the data that is stored in the first partition, the one or more links organized according to metadata associated with the one or more tags.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.

Abstract: A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract: A system for using bad blocks in a memory system is proposed. The system includes accessing an identification of a plurality of bad blocks and corresponding error codes which, for example, were generated during a manufacturing test and stored on the memory integrated circuit. The system determines which blocks of the plurality of bad blocks to test for being still usable and which blocks of the plurality of bad blocks not to test for being still usable based on corresponding error codes. For each bad block that should be tested, a test from a plurality of tests is chosen based on the corresponding error code in order to determine if the bad block is still usable. Those blocks determined to be still usable are subsequently used to store non-mission critical information.

Abstract: A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature to all or a subset of the dummy memory cells as part of a memory operation.

Abstract: A storage system and method for improved command flow are provided. In one embodiment, a storage system receives a request from a host for an indication of which command(s) stored in the storage system are ready for execution; in response to the request, provides the host with the indication of which command(s) stored in the storage system are ready for execution; receives an instruction from the host to execute a command that is ready for execution; and in response to the instruction from the host to execute the command, performs both of the following: executes the command and provides the host with an updated indication of which command(s) stored in the storage system are ready for execution, wherein the storage system provides the host with the updated indication without receiving a separate request from the host for the updated indication. Other embodiments are provided.

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.

Abstract: A storage device with a memory may implement command throttling in order to control power usage. The throttling may be based on modifications of certain memory parameters, such as a reduction in clock rate, bus speed, operating voltage, or command type changes. The throttling may be performed at a back end or memory interface of the storage device such that the memory interface receives un-throttled commands and can optimally throttle all of the commands from the front end.

Abstract: A storage system and method for recovering data corrupted in a host memory buffer are provided. In one embodiment, a storage system is provided comprising a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to receive a logical-to-physical map from a volatile memory of a host for storage in the storage system's non-volatile memory; determine if there is an error in an entry in the logical-to-physical map; in response to determining that there is no error in the logical-to-physical map, store the logical-to-physical map in the non-volatile memory; and in response to determining that there is an error in an entry in the logical-to-physical map, attempt to recover the entry from a location in the storage system before storing the logical-to-physical map in the non-volatile memory. Other embodiments are provided.

Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.

Abstract: A system and method for compacting data in a non-volatile memory system that may reduce the need for control data updates is described. The method may include copying valid data from a source block to a destination block, and also writing new host data to the destination block, such that the offset position in the destination block of the copied data is the same as in the source block and fewer mapping table updates are needed for the copied data. The system may include a non-volatile memory system with a coarse granularity mapping table and a fine granularity mapping table where a controller in the non-volatile memory system is configured to only update the coarse granularity mapping table for compacted data written to a new block, but is configured to update both the fine and coarse granularity mapping tables for new host data written to the new block.

Abstract: A storage device may utilize a host memory buffer for re-ordering commands in a submission queue. Out of order commands in a submission queue that uses host virtual buffers that are not the same size may be difficult to search. Accordingly, commands in a submission queue may be correctly ordered in a host memory buffer before being put into the host virtual buffers. When the commands are in order, the search operation for specific data is improved.