Abstract: A data storage device includes one or more memory device and a controller that is DRAM-less coupled to the one or more memory devices. The controller is configured to receive a command from a host device, begin execution of the command, and receive an abort request command for the command. The command includes pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.

Abstract: Embodiments of the present disclosure generally relate to housings for, e.g., memory devices and electronic devices, and to processes for forming such housings. In an embodiment, an article for housing at least a portion of an electronic device is provided. The article includes a first component comprising a thermoplastic and a biodegradable filler or polymer, and a second component disposed on at least a portion of the first component, the second component comprising a plurality of layers. The article has a scratch visibility load of about 200 gms or more, an electrostatic discharge static voltage of about 100 V or less, a thermal conductivity of about 0.28 W/mK or more, or combinations thereof.

Abstract: A data storage device includes a substrate and one or more grid array integrated circuit packages. The grid array integrated circuit package includes at least one self-alignment pin having a tapered shape. The substrate includes one or more connection pads to receive the grid array integrated circuit packages. The connection pads include at least one self-alignment receptacle that receives the self-alignment pins such that the grid array integrated circuit packages maintain an alignment with an associated connection pad of the substrate.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a first three-dimensional memory array located in a first memory array region, and a second three-dimensional memory array located in a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by an inter-array region. The alternating stack is laterally bounded by two trench fill structures that are laterally spaced apart along a second horizontal direction by an inter-trench spacing. The inter-array region includes a stepped cavity having vertical steps of the alternating stack that laterally extend along different horizontal directions. Multiple rows of contact via structures may contact different electrically conductive layers in the stepped cavity.

Abstract: A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

Abstract: A memory device includes a memory block with memory cells that are arranged in word lines. Control circuitry in the memory device selects a word line to program; sets a programming pulse voltage to a starting value; and determines an operating temperature and compares the operating temperature to a first threshold temperature. In response to the operating temperature being less than the first threshold temperature, the control circuitry sets a program voltage step size to a baseline. In response to the operating temperature being greater than a first threshold temperature, the control circuitry sets the program voltage step size to a high temperature step size that is less than the baseline step size. The control circuitry programs the selected word line. Each program loop includes a programming pulse, and the control circuitry increases a magnitude of the programming pulse between program loops by the program voltage step size.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a first backside trench fill structure and a second backside trench fill structure. Each of the electrically conductive layers includes a respective metal nitride liner and a respective metal fill material region. The respective metal fill material region includes a respective first-thickness portion having a respective first vertical thickness and a respective second-thickness portion having a respective second vertical thickness that is greater than the respective first vertical thickness.

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip.

Abstract: A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Abstract: Technology is disclosed herein for early erase termination as a counter-measure for erase disturb. Multiple erase blocks of NAND memory cells are erased in parallel during an erase procedure. Erasing multiple erase blocks in parallel can place considerable strain on the circuitry that generates the erase voltage. If there is significant leakage current in one of the erase blocks the magnitude of the erase voltage for all of the erase blocks may drop. The erase blocks are tested sequentially for leakage current during the first erase loop while the erase voltage is applied to only the erase block under test. If any erase block fails the leakage current test that erase block is removed from the erase procedure. One or more additional erase loops are then performed with only those erase blocks that passed the leakage current test simultaneously receiving an erase voltage, thereby preventing erase disturb with early termination.

Abstract: This disclosure relates to systems, methods, and data storage devices, such as a data storage device comprising a data path and a controller. The data path comprises a data port to transmit data between a host computer system and the data storage device. The data storage device registers with the host computer system as a block data storage device. A non-volatile storage medium stores encrypted user content data. A cryptography engine is connected between the data port and the storage medium and uses cryptographic key data to encrypt and decrypt user content data. The controller is configured to send the encrypted user content data for back-up storage external to the data storage device as encrypted by the cryptographic key data, and communicate with a user device over a communication channel that is different from the data path, to send the cryptographic key data for decryption of the encrypted user content external to the data storage device.

Abstract: A memory device includes at least one alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface; and one of the electrically conductive layers is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.

Abstract: An etching method includes etching a material in an etch chamber by alternating normal-flow etch steps and reduced-flow etch steps, where an etchant gas is provided at a normal flow rate into the etch chamber during the normal-flow etch steps, and the etchant gas is provided at a reduced flow rate lower than the normal flow rate into the etch chamber during the reduced-flow etch steps, obtaining optical emission spectroscopy (OES) data during the reduced-flow etch steps, determining an end point for the etching based on the obtained OES data, and ending the etching at the determined end point.

Abstract: A die separation ring that causes non-uniform expansion of a semiconductor wafer during a semiconductor wafer expansion process. The die separation ring includes an annular body that extends about a central axis. The annular body of the die separation ring includes a first portion having a first elevation and a second portion having a second elevation that is lower than the first elevation. A third portion extends between the first portion and the second portion forming a transition between the first portion and the second portion.

Abstract: The present disclosure generally relates to improved optimization of a cache lookup operation by structuring the write cache buffers differently using a link-list. Rather than executing a read command first and then executing a write command only after the read command is executed, this disclosure suggests reordering the command executions. A device waits before executing the read command giving the opportunity to obtain the overlap write command. The device then reorders the command execution and executes first the write command and then executes the read command by accessing the write cache instead of the NAND. When two write commands need to be executed consecutively, the link-list operation is used. The controller finds the relevant buffer in the cache that is needed and overwrites the buffer with the new data. The new data is then written to the cache without accessing the cache multiple times.

Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing and first metallic bonding structures and a first dielectric capping layer containing openings and contacting distal horizontal surfaces of the first metallic bonding structures, providing a second semiconductor die containing second metallic bonding structures, disposing the second semiconductor die in contact with the first semiconductor die, and annealing the second semiconductor die in contact with the first semiconductor die such that a metallic material of at least one of the first metallic bonding structures and the second metallic bonding structures expands to fill the openings in the first dielectric capping layer to bond at least a first subset of the first metallic bonding structures to at least a first subset of the second metallic bonding structures.

Abstract: A lead finger has a v-shaped contact point and a u-shaped profile. The u-shaped profile includes a portion that is disposed below a top surface of a PCB. The v-shaped contact point aids in guiding a host connector clip to an ideal location of the lead finger, where the ideal location may allow for more contact surface area and better contact to the host connector clip. The u-shaped profile may reduce impact force of the host connector clip to the lead finger.

Abstract: When copy commands are queued in a submission queue, there can potentially be many queued input-output (I/O) commands directed to the same logical range as the queued commands. This can result in data being invalidated immediately after it is written in memory, leading to write amplification and inefficient backend processing. To address this problem, the embodiments presented herein can be used to lock the range of logical block addresses of the queued commands, so that I/O commands are prevented from accessing the range of logical block addresses until the queued copy commands are completed.

Abstract: A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material l

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip.