Abstract: The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.

Abstract: A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate either a CMB buffer or a HMB buffer based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. By leveraging the benefits of both the CMB and the HMB to store data, the overall performance of the data storage device may be improved.

Abstract: A vehicle battery includes at least one battery cell and a battery controller for charging the at least one battery cell via a power interface of the vehicle battery. The vehicle battery further includes a battery memory and a data interface to transfer data between the battery memory and a data device external to the vehicle. A data storage controller of the vehicle battery transfers, via the data interface, data between the battery memory and the data device while the vehicle battery is removed from the vehicle. In one aspect, the data device performs at least one of transferring data from a battery memory to a memory of the data device and transferring data from the memory of the data device to the battery memory while the data device is physically connected to the vehicle battery.

Abstract: A data storage device includes storage media and control circuitry and is configured to enable the creation of partitions with different performance levels. The storage media includes a first set and a second set of memory blocks having different performance levels. The control circuitry is configured to: in response to a request from a host system, provide performance data from the first set of memory blocks and the second set of memory blocks to the host system. The control circuitry is further configured to: receive partition settings from the host system, the partition settings creating a first partition including at least part of the first set of memory blocks and a second partition including at least part of the second set of memory blocks, wherein the first partition has a better performance level than the second partition; and save the partition settings to the storage media.

Abstract: A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.

Abstract: An apparatus is provided that includes a memory structure including non-volatile memory cells, a first processor and a second processor. The first processor is configured to provide a plurality of sets of commands to a second processor to perform memory operations on the non-volatile memory cells. The second processor is configured to execute the sets of commands and provide a control signal to the first processor. The first processor is further configured to provide the sets of commands to the second processor based on a status of the control signal. The second processor is further configured to control the status of the control signal so that the second processor executes sets of commands with no idle time between consecutive sets of commands.

Abstract: The disclosure relates in some aspects to an apparatus that includes stages of a failure event counting circuit including an Nth stage where N refers to an arbitrary stage of the stages of the failure event counting circuit. The Nth stage may include an Nth fuse trigger circuit configured to receive an event detector signal indicative of a failure event, an Nth electronic fuse configured to disconnect a circuit path between a voltage source and a ground in response to the event detector signal, and an Nth delay circuit coupled to the Nth e-fuse and configured to cause a time delay for activating a subsequent stage of the failure event counting circuit in response to the Nth e-fuse disconnecting. In this aspect, each of the stages of the failure event counting circuit may be configured to use the respective e-fuse to record a discrete failure event.

Abstract: The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive learning process based upon statistic collection of SGL fetches. By maintaining a table of statistics, the data storage device controller may learn and more closely predict an amount of memory to allocate for SGL fetching.

Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.

Abstract: A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.

Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

Abstract: There is a large latency and controller bandwidth associated with moving data between dies or between memory devices. The controller includes one or more flash interface modules (FIMs) that are utilized to write data to the memory device and read data from the memory device. Each of the one or more FIMs includes one or more switches. Each switch is utilized to transfer data from a source block to a destination block. Likewise, rather than using a memory external to the FIM to cache the data, the data is stored in a FIM cache and moved from the FIM cache to the relevant physical layer to be programmed to the destination block. Because data is not being transferred to the system memory, the latency and bandwidth associated with relocating data may be decreased.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.

Abstract: Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a threshold voltage after the ramp-up period. If the erase voltage is below the threshold voltage after the ramp-up period then the erase block may be marked as defective. If the erase voltage is above the threshold voltage after the ramp-up period then the erase block may be marked as good.

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

Abstract: A storage device minimizes HPB entry inactivation resulting from data associated with hot reads being retrieved from multiple HPB sub-regions covering a logical-to-physical table. The storage device may support the HPB feature and a multiple HPB sub-region mode. The storage device includes a controller that tracks a hit count associated with a logical block address in a read command. The controller determines that the hit count has reached a hit threshold and updates a hit table to identify logical block address pages associated with hit counts that have reached the hit threshold across HPB sub-regions covering a logical-to-physical table. The controller transmits the hit table to a host device to be stored in an HPB cache on the host device and to be used by the host device for read commands sent from the host device to the storage device.

Abstract: A data storage device and method for host-assisted improved error recovery using a correlation factor are provided. In one embodiment, the data storage device receives, from a host, an indication that data associated with a first logical address is correlated with data associated with a second logical address; determines a correlation factor based on a degree of correlation between the data associated with the first logical address and the data associated with the second logical address; and in response to the correlation factor being above a threshold: stores the data associated with the first logical address and the data associated with the second logical address in different regions of the memory having different bit error rates; and uses the data associated with the first logical address to assist in correcting an error in the data associated with the second logical address. Other embodiments are provided.

Abstract: A method of forming a semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor device.

Abstract: A network attached storage device coupled to a local network and including a network interface configured to receive digital content from a remote content provider outside the local network. The network attached storage device includes storage having a first region accessible by a user of the local network and a secure region. The network attached storage device includes a processor coupled to the storage, the processor configured to control access to the secure region of the storage based on instructions received from a remote content provider.

Abstract: A data storage device and method are provided for performing an action on an area of memory to satisfy a host-provided target operating condition. In one embodiment, a controller of the data storage device is configured to: receive, from a host, an identification of an area of the memory and a target operating condition for the area of the memory; monitor the area of the memory to determine whether the area of the memory satisfies the target operating condition; and in response to determining that the area of the memory does not satisfy the target operating condition, perform an action on the area of the memory to attempt to cause the area of the memory to satisfy the target operating condition. Other embodiments are provided, and each of the embodiments can be used alone or in combination.