Abstract: In response to receiving a request to perform a transaction with two or more memory operations on one or more tiered data structures, the memory controller: writes a start transaction record to the log stream including a transaction identifier corresponding to the transaction; and performs the two or more memory operations. For a first memory operation associated with a key, the memory controller: writes a new data object in a datastore; assigns, in a key-map, a location of the new data object to the key; maintains an old data object in the datastore whose location was previously assigned to the key; and writes an operation commit record to a log stream upon completion of the first memory operation. In accordance with a determination that the two or more memory operations are complete, the memory controller writes a transaction commit record to the log stream including the transaction identifier.

Abstract: In an electronics system, an adjustable airflow guide assembly and methods of deploying it facilitate dissipating heat. The assembly includes an extendable plate having a first coupling capable of rotatably attaching the extendable plate to a chassis, a link, including a second coupling, capable of translatably attaching the link to the chassis, and a third coupling capable of rotatably attaching the link to the extendable plate. The extendable plate presents a guide to deflect airflow and is capable of being swung into multiple different fixed positions to divert airflow within the electronics system toward portions of the chassis configured with electronic components that produce heat, such as board solid state drives (BSSDs).

Abstract: A storage system, and a method of data management in the storage system, with non-volatile memory device characteristics determined during an inspection of non-volatile memory devices before a runtime operation of a storage device in the storage system including: a controller in the storage system: a drive-level control unit configured for an update of operational capabilities based on the non-volatile memory device characteristics during the runtime operation of the storage device and for a group of the non-volatile memory devices based on the operational capabilities; and a memory control unit, coupled to the drive-level control unit, the memory control unit configured to receive the operational capabilities for control of the non-volatile memory devices.

Abstract: The various implementations described herein include systems, methods and/or devices used to manage heat flow for dissipating heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one embodiment, heat sinks are disposed on front sides of a first module and a second module in the electronic system, and at least one heat sink in the second module is disposed between at least two heat sinks in the first module. In some embodiments, the number of heat sinks and/or a subset of geometric parameters for the locations, sizes and shapes of the heat sinks are configured for the purpose of disturbing and mixing air flow that passes an air gap between the front sides of the first and second modules.

Abstract: Various embodiments described herein disclose systems, methods and/or devices used to dissipate heat generated by electronic components of an electronic assembly that further includes a first assembly rail, a top circuit board and a bottom circuit board. The first assembly rail includes a first card guide structure and a second card guide structure that are arranged on a first side of the first assembly rail near two opposite ends of the assembly rail. The top and the bottom circuit boards are mechanically coupled to the first and second card guide structures of the first assembly rail, respectively. The top circuit board is parallel to the bottom circuit board, and separated from the bottom circuit board by a predefined distance. The first assembly rail, the top circuit board and the bottom circuit board together form a channel there between for receiving a heat dissipating airflow.

Abstract: Various embodiments described herein include systems, methods and/or devices used to dissipate heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board with one or more heat generating components coupled thereto. The electronic assembly further includes a second circuit board with one or more heat sensitive components coupled thereto. The electronic assembly also includes a thermal barrier interconnect. The thermal barrier interconnect electrically couples the first circuit board to the second circuit board. In some embodiments, thermal barrier interconnect is a flexible interconnect with a lower thermal conductivity than the first circuit board and the second circuit board. The thermal barrier interconnect forms a thermal barrier between the first and second circuit boards which protects the heat sensitive components from the heat generating components.

Abstract: Various embodiments described herein include systems, methods and/or devices for dissipating heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board, a second circuit board flexibly coupled to the first circuit board, a connecting module coupled to the second circuit board, and a fastener. The fastener is configured to couple the first circuit board to the connecting module such that the first circuit board and the second circuit board are substantially parallel and are separated by a space, wherein the space forms at least part of a channel that is configured to direct airflow through the space between the first circuit board, second circuit board, and connecting module.

Abstract: The system for redirecting airflow includes multiple electronic assemblies arranged adjacent to one another. Each electronic assembly includes a substrate having a substantially flat first surface and an opposing substantially flat second surface. Electronic devices are coupled to each of the first and second surfaces. Each surface also has one or more tabs coupled thereto, where each tab is configured to redirect the airflow over a least one electronic device.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable dynamic brownout adjustment in a storage device. In one aspect, the method includes: (1) obtaining a set of power tolerance settings, the set of power tolerance settings used for determining whether one or more power supply voltages provided to the storage device are out of range, (2) in response to a predefined trigger, adjusting the set of power tolerance settings in accordance with one or more parameters of the storage device, (3) determining, in accordance with the adjusted set of power tolerance settings, whether the one or more power supply voltages are out of range, and (4) in accordance with a determination that the one or more power supply voltages are out of range, latching a power fail condition.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable power inrush management of storage devices (e.g., DIMM devices). In one aspect, the method includes, for at least one storage device populated in a slot of a plurality of storage device slots, the plurality of storage device slots configured to be populated by two or more storage devices: (1) detecting a unique location associated with the storage device, (2) determining a time delay for the storage device in accordance with the unique location associated with the storage device, and (3) delaying at least one power-on operation of the storage device by the time delay for the storage device.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. The method includes performing a set of second stage operations including storing, in the first set of memory blocks, first and second sets of metadata, encrypted using the second encryption key. The method includes performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key. The method includes setting the second encryption key as the current encryption key for the plurality of memory blocks.

Abstract: The various implementations described herein include systems, methods and/or devices used to protect data in a storage device. In one aspect, a method includes (1) powering a power control processor (PCP) (also sometimes called a storage-level microcontroller) using a first input voltage, (2) while the PCP is powered using the first input voltage: (a) operating the PCP in a first mode, and (b) enabling charging of an energy storage device, (3) after achieving a predefined internal state, which includes the energy storage device charged to a predefined level, powering the PCP using a power supply voltage distinct from the first input voltage, and (4) while the PCP is powered using the power supply voltage, operating the PCP in a second mode, where the PCP operates at a higher performance level in the second mode than in the first mode.

Abstract: The various implementations described herein include systems, methods and devices used to protect data in a storage device. In one aspect, a method includes, performing a soft power fail operation on a section of the device, the operation including: (1) signaling a power test condition to a first controller on the storage device; (2) providing one or more controllers with power from an energy storage device, where the energy storage device is distinct from a power supply used during normal operation; (3) signaling a power fail condition to the one or more controllers on the storage device, where the one or more controllers communicate with the first controller and correspond to said section of the storage device, and where, in response to the power fail condition, each of the one or more controllers performs a data hardening operation; and (4) resuming normal operation on said section of the storage device.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable performing supervisory functions for a dual in-line memory module (DIMM), at a controller in the DIMM. The method includes upon power-up, determining a power supply voltage provided to the DIMM. In accordance with a determination that power supply criteria are satisfied, the method includes: (1) performing one or more power-up operations, including initiating a usage counter, (2) monitoring a temperature of the DIMM, (3) monitoring the DIMM for occurrence of one or more of a set of predetermined trigger events, and (4) in response to detecting one of the set of predetermined trigger events, logging information corresponding to the detected predetermined event.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is higher than an over-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is higher than the over-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable power fail latching based on monitoring multiple power supply voltages in a storage device. In one aspect, the method includes: (1) determining whether a first power supply voltage provided to the storage device is out of range for a first time period, (2) determining whether a second power supply voltage provided to the storage device is out of range for a second time period, and (3) in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable adaptive erasure in a storage device. The method includes performing a plurality of memory operations including read operations and respective erase operations on portions of one or more non-volatile memory devices specified by the read operations and respective erase operations, where the respective erase operations are performed using a first set of erase parameters that has been established as a current set of erase parameters prior to performing the respective erase operations. The method includes, in accordance with each erase operation of at least a subset of the respective erase operations, updating one or more erase statistics that correspond to performance of multiple erase operations. The method includes, in accordance with a comparison of the erase statistics with an erasure performance threshold, establishing a second set of erase parameters as the current set of erase parameters.

Abstract: The embodiments described herein are methods and systems to enhance the reliability and performance of a persistent datastore (e.g., non-volatile memory such as flash memory). The method includes generating a log entry associated with first write data. The method also includes generating a first record including the log entry, the first write data, and pointer to a second record different from the first record. The method further includes performing a single write operation that includes writing the first record to the persistent datastore.

Abstract: A system and method of data management with modular erase in a data storage system with a memory array having an erase block and a target block with the target block in a logical unit separate from the erase block including: performing an erase operation on the erase block, the erase operation having an operation matrix configured for partial erasing of the erase block; updating a command status for the erase block; enabling an intervening command on the target block based on the command status indicating an incomplete erase status with the intervening command updating the command status; performing an erase optimization based on the command status; performing an additional erase operation based on the erase optimization; and updating the command status to an erase complete status based on the additional erase operation.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, a method includes, in response to a first signal received by the storage device, performing a soft power fail operation on a first section of the storage device. The soft power fail operation including: (1) signaling a power fail condition to a first plurality of controllers on the storage device, where the first plurality of controllers correspond to the first section of the storage device, (2) transferring data held in volatile memory of the storage device to non-volatile memory of the storage device, and (3) removing power from the first plurality of controllers.