Abstract: In response to receiving a request to perform a transaction with two or more memory operations on one or more tiered data structures, the memory controller: writes a start transaction record to the log stream including a transaction identifier corresponding to the transaction; and performs the two or more memory operations. For a first memory operation associated with a key, the memory controller: writes a new data object in a datastore; assigns, in a key-map, a location of the new data object to the key; maintains an old data object in the datastore whose location was previously assigned to the key; and writes an operation commit record to a log stream upon completion of the first memory operation. In accordance with a determination that the two or more memory operations are complete, the memory controller writes a transaction commit record to the log stream including the transaction identifier.

Abstract: In an electronics system, an adjustable airflow guide assembly and methods of deploying it facilitate dissipating heat. The assembly includes an extendable plate having a first coupling capable of rotatably attaching the extendable plate to a chassis, a link, including a second coupling, capable of translatably attaching the link to the chassis, and a third coupling capable of rotatably attaching the link to the extendable plate. The extendable plate presents a guide to deflect airflow and is capable of being swung into multiple different fixed positions to divert airflow within the electronics system toward portions of the chassis configured with electronic components that produce heat, such as board solid state drives (BSSDs).

Abstract: A storage system, and a method of data management in the storage system, with non-volatile memory device characteristics determined during an inspection of non-volatile memory devices before a runtime operation of a storage device in the storage system including: a controller in the storage system: a drive-level control unit configured for an update of operational capabilities based on the non-volatile memory device characteristics during the runtime operation of the storage device and for a group of the non-volatile memory devices based on the operational capabilities; and a memory control unit, coupled to the drive-level control unit, the memory control unit configured to receive the operational capabilities for control of the non-volatile memory devices.

Abstract: Various embodiments described herein include systems, methods and/or devices used to dissipate heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic assembly includes a first circuit board with one or more heat generating components coupled thereto. The electronic assembly further includes a second circuit board with one or more heat sensitive components coupled thereto. The electronic assembly also includes a thermal barrier interconnect. The thermal barrier interconnect electrically couples the first circuit board to the second circuit board. In some embodiments, thermal barrier interconnect is a flexible interconnect with a lower thermal conductivity than the first circuit board and the second circuit board. The thermal barrier interconnect forms a thermal barrier between the first and second circuit boards which protects the heat sensitive components from the heat generating components.

Abstract: A method of bandwidth optimization in a non-volatile memory system includes: retrieving hard data bits; generating soft information from the hard data bits; applying a lossless compression to the soft information for calculating syndrome bits; and executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and a data hardening module in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is lower than an under-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is lower than the under-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device.

Abstract: A method of caching data is performed by a respective computer having one or more processors storing one or more storage management programs for execution by the one or more processors, non-volatile secondary storage and non-volatile cache memory. The method includes receiving from the non-volatile cache memory information identifying an amount of available storage in the non-volatile cache memory, and identifying a size of the management units in the non-volatile cache memory. The method further includes identifying write requests to write data to the non-volatile cache memory, sequentially writing to the non-volatile cache memory the write data for the identified write requests, to sequentially arranged locations in an address space of the non-volatile cache memory, and storing in memory metadata that maps the addresses or storage offsets of the write data to respective locations in the address space of the non-volatile cache memory.

Abstract: Systems, methods and/or devices are used to adapt a target charge to equalize bit errors across page types for a storage medium, such as flash memory, in a storage system. In one aspect, the method includes performing a sequence of operations, including: (1) determining a first target charge, a second target charge, and a third target charge, the first, second, and third target charges used for controlling first, second, and third charge distributions, respectively, in cells of the storage medium when data is written to the cells, wherein the second charge distribution is between the first charge distribution and the third charge distribution, (2) determining a first error indicator for lower/fast pages of the storage medium, (3) determining a second error indicator for upper/slow pages of the storage medium, and (4) adjusting the second target charge in accordance with the first error indicator and the second error indicator.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable biasing for wear leveling in storage systems. In one aspect, the method includes (1) determining, for each erase unit of a plurality of erase units in the storage medium, an age metric, (2) determining a representative age metric of the plurality of erase units, (3) for each respective erase unit of the plurality of erase units, biasing a respective garbage collection control metric for the respective erase unit in accordance with the age metric of the respective erase unit in relation to the representative age metric of the plurality of erase units to generate an adjusted garbage collection control metric for the respective erase unit, and (4) performing garbage collection for the storage medium in accordance with the adjusted garbage collection control metrics of the plurality of erase units.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable power fail latching based on monitoring multiple power supply voltages in a storage device. In one aspect, the method includes: (1) determining whether a first power supply voltage provided to the storage device is out of range for a first time period, (2) determining whether a second power supply voltage provided to the storage device is out of range for a second time period, and (3) in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition.

Abstract: The embodiments described herein include a method and device for adjusting trip points within a storage device. The method includes: obtaining one or more configuration parameters; and based on the one or more configuration parameters, determining a trip voltage. The method also includes comparing the trip voltage with an input voltage. The method further includes triggering a power fail condition in accordance with a determination that the input voltage is less than the trip voltage.

Abstract: The various implementations described herein include systems, methods and devices used to protect data in a storage device. In one aspect, a method includes, performing a soft power fail operation on a section of the device, the operation including: (1) signaling a power test condition to a first controller on the storage device; (2) providing one or more controllers with power from an energy storage device, where the energy storage device is distinct from a power supply used during normal operation; (3) signaling a power fail condition to the one or more controllers on the storage device, where the one or more controllers communicate with the first controller and correspond to said section of the storage device, and where, in response to the power fail condition, each of the one or more controllers performs a data hardening operation; and (4) resuming normal operation on said section of the storage device.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, a method includes, in response to a first signal received by the storage device, performing a soft power fail operation on a first section of the storage device. The soft power fail operation including: (1) signaling a power fail condition to a first plurality of controllers on the storage device, where the first plurality of controllers correspond to the first section of the storage device, (2) transferring data held in volatile memory of the storage device to non-volatile memory of the storage device, and (3) removing power from the first plurality of controllers.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. The method includes obtaining symbol transition information corresponding to symbol read errors identified while reading data from flash memory cells in a flash memory device. The method further includes determining a reading threshold voltage offset, based at least in part on: a plurality of probability values determined from the symbol transition information; a current count of program-erase cycles; and a word line zone value for a word line zone containing the flash memory cells. Additionally, the method includes generating an updated reading threshold voltage in accordance with the reading threshold voltage offset and the current value of the reading threshold voltage.

Abstract: A storage controller has multiple processors, divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In some embodiments, the storage controller operates with a flash memory module, and includes a first processor group, a second processor group and a third processor group, each having one or more processors for handling a different stage of a pipelined execution of host storage commands. With respect to a first host command, a first processor of the first processor group, a first processor of the second processor group, and a first processor of the third processor group comprise a first pipeline, and with respect to a second host command, a second processor of the first processor group, a second processor of the second processor group, and a second processor of the third processor group comprise a second pipeline.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. Some implementations include a method of compressing a sequence of read data values into a bit-tuple of a predefined length to enable soft information decoding systems that use less power and/or less memory. In some implementations, the bit-tuple of a predefined length is produced using M single-bit buffer locations, where M corresponds to the predefined length of the bit-tuple. Some implementations utilize a collection of characterization vectors that include soft information values associated with the possible permutations of the bit-tuples. In turn, a sequence of bit-tuples is converted into a sequence of soft information values by retrieving a particular characterization vector, and selecting a respective soft information value from that characterization vector for each bit-tuple in the sequence.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable write amplification reduction by delaying read access to data written during garbage collection. In one aspect, read access to a write unit to which data was written during garbage collection is delayed until a predefined subsequent operation has been completed.

Abstract: The various implementations described herein include systems, methods and/or devices used to protect data in a storage device. In one aspect, a method includes (1) powering a power control processor (PCP) (also sometimes called a storage-level microcontroller) using a first input voltage, (2) while the PCP is powered using the first input voltage: (a) operating the PCP in a first mode, and (b) enabling charging of an energy storage device, (3) after achieving a predefined internal state, which includes the energy storage device charged to a predefined level, powering the PCP using a power supply voltage distinct from the first input voltage, and (4) while the PCP is powered using the power supply voltage, operating the PCP in a second mode, where the PCP operates at a higher performance level in the second mode than in the first mode.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance performance of error control encoding. The method includes receiving information data and generating parity information based on an m×k parity matrix comprising an array of b×b circulant sub-matrices, including m columns of said sub-matrices, each column comprising k said sub-matrices. The method further includes dividing the information data into a plurality of b-sized trunks and generating m parity segments. Each parity segment consists of b bits, and each parity segment is generated by multiplying each of the k b×b circulant sub-matrices in a respective column of the parity matrix by a corresponding trunk of information data, where each multiplication of a b×b circulant sub-matrix by a corresponding trunk comprises b2 concurrent computations. The method further includes generating a codeword based on the information data and the m parity segments.

Abstract: A method for improving data integrity in a non-volatile memory system includes: accessing a non-volatile memory cell for retrieving hard data bits; generating soft information by capturing a reliability of the hard data bits; calculating syndrome bits by applying a lossy compression to the soft information; and generating a host data by executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits.