Abstract: The system for redirecting airflow includes multiple electronic assemblies arranged adjacent to one another. Each electronic assembly includes a substrate having a substantially flat first surface and an opposing substantially flat second surface. Electronic devices are coupled to each of the first and second surfaces. Each surface also has one or more tabs coupled thereto, where each tab is configured to redirect the airflow over a least one electronic device.

Abstract: Mechanisms are provided for detecting whether at least one of two or more portions of memory (e.g. chips, blocks, sectors, planes, pages, word lines, etc.) are more error-prone than the others, when portions of codewords are interleaved across the two or more portions of memory. Some implementations also enable various remedial operations that can be selectively employed in response to detecting an unbalanced error condition in order to reduce the risks associated with interleaving portions of codewords across two or more portions of memory.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. The method includes performing a set of second stage operations including storing, in the first set of memory blocks, first and second sets of metadata, encrypted using the second encryption key. The method includes performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key. The method includes setting the second encryption key as the current encryption key for the plurality of memory blocks.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable dynamic brownout adjustment in a storage device. In one aspect, the method includes: (1) obtaining a set of power tolerance settings, the set of power tolerance settings used for determining whether one or more power supply voltages provided to the storage device are out of range, (2) in response to a predefined trigger, adjusting the set of power tolerance settings in accordance with one or more parameters of the storage device, (3) determining, in accordance with the adjusted set of power tolerance settings, whether the one or more power supply voltages are out of range, and (4) in accordance with a determination that the one or more power supply voltages are out of range, latching a power fail condition.

Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that use error control codes to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. The method includes performing a set of second stage operations including storing, in the first set of memory blocks, first and second sets of metadata, encrypted using the second encryption key. The method includes performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key. The method includes setting the second encryption key as the current encryption key for the plurality of memory blocks.

Abstract: The various implementations described herein include systems, methods and devices used to protect data in a storage device. In one aspect, a method includes, performing a soft power fail operation on a section of the device, the operation including: (1) signaling a power test condition to a first controller on the storage device; (2) providing one or more controllers with power from an energy storage device, where the energy storage device is distinct from a power supply used during normal operation; (3) signaling a power fail condition to the one or more controllers on the storage device, where the one or more controllers communicate with the first controller and correspond to said section of the storage device, and where, in response to the power fail condition, each of the one or more controllers performs a data hardening operation; and (4) resuming normal operation on said section of the storage device.

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable power inrush management of storage devices (e.g., DIMM devices). In one aspect, the method includes, for at least one storage device populated in a slot of a plurality of storage device slots, the plurality of storage device slots configured to be populated by two or more storage devices: (1) detecting a unique location associated with the storage device, (2) determining a time delay for the storage device in accordance with the unique location associated with the storage device, and (3) delaying at least one power-on operation of the storage device by the time delay for the storage device.

Abstract: The various implementations described herein include systems, methods and/or devices used to protect data in a storage device. In one aspect, a method includes (1) powering a power control processor (PCP) (also sometimes called a storage-level microcontroller) using a first input voltage, (2) while the PCP is powered using the first input voltage: (a) operating the PCP in a first mode, and (b) enabling charging of an energy storage device, (3) after achieving a predefined internal state, which includes the energy storage device charged to a predefined level, powering the PCP using a power supply voltage distinct from the first input voltage, and (4) while the PCP is powered using the power supply voltage, operating the PCP in a second mode, where the PCP operates at a higher performance level in the second mode than in the first mode.

Abstract: An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments.

Abstract: Approaches for a distributed storage system that comprises a plurality of nodes. Each node, of the plurality of nodes, executes one or more application processes which are capable of accessing persistent shared memory. The persistent shared memory is implemented by solid state devices physically maintained on each of the plurality of nodes. Each the one or more application processes, maintained on a particular node, of the plurality of nodes, communicates with a shared data fabric (SDF) to access the persistent shared memory. The persistent shared memory comprises a scoreboard implemented in shared DRAM memory that is mapped to a persistent storage. The scoreboard provides a crash tolerant mechanism for enabling application processes to communicate with the shared data fabric (SDF).

Abstract: The various embodiments described herein include systems, methods and/or devices used to enable power fail latching based on monitoring multiple power supply voltages in a storage device. In one aspect, the method includes: (1) determining whether a first power supply voltage provided to the storage device is out of range for a first time period, (2) determining whether a second power supply voltage provided to the storage device is out of range for a second time period, and (3) in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable adaptive erasure in a storage device. The method includes performing a plurality of memory operations including read operations and respective erase operations on portions of one or more non-volatile memory devices specified by the read operations and respective erase operations, where the respective erase operations are performed using a first set of erase parameters that has been established as a current set of erase parameters prior to performing the respective erase operations. The method includes, in accordance with each erase operation of at least a subset of the respective erase operations, updating one or more erase statistics that correspond to performance of multiple erase operations. The method includes, in accordance with a comparison of the erase statistics with an erasure performance threshold, establishing a second set of erase parameters as the current set of erase parameters.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable performing supervisory functions for a dual in-line memory module (DIMM), at a controller in the DIMM. The method includes upon power-up, determining a power supply voltage provided to the DIMM. In accordance with a determination that power supply criteria are satisfied, the method includes: (1) performing one or more power-up operations, including initiating a usage counter, (2) monitoring a temperature of the DIMM, (3) monitoring the DIMM for occurrence of one or more of a set of predetermined trigger events, and (4) in response to detecting one of the set of predetermined trigger events, logging information corresponding to the detected predetermined event.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is higher than an over-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is higher than the over-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable multipass programming in buffers implemented in non-volatile data storage systems (e.g., using one or more flash memory devices). In one aspect, a portion of memory (e.g., a page in a block of a flash memory device) may be programmed many (e.g., 1000) times before an erase is required. Some embodiments include systems, methods and/or devices to integrate Bloom filter functionality in a non-volatile data storage system, where a portion of memory storing one or more bits of a Bloom filter array may be programmed many (e.g., 1000) times before the contents of the portion of memory need to be moved to an unused location in the memory.

Abstract: A system and method of data management with modular erase in a data storage system with a memory array having an erase block and a target block with the target block in a logical unit separate from the erase block including: performing an erase operation on the erase block, the erase operation having an operation matrix configured for partial erasing of the erase block; updating a command status for the erase block; enabling an intervening command on the target block based on the command status indicating an incomplete erase status with the intervening command updating the command status; performing an erase optimization based on the command status; performing an additional erase operation based on the erase optimization; and updating the command status to an erase complete status based on the additional erase operation.

Abstract: The embodiments described herein are methods and systems to enhance the reliability and performance of a persistent datastore (e.g., non-volatile memory such as flash memory). The method includes generating a log entry associated with first write data. The method also includes generating a first record including the log entry, the first write data, and pointer to a second record different from the first record. The method further includes performing a single write operation that includes writing the first record to the persistent datastore.

Abstract: A method of operation of a data storage system includes: monitoring a data interface bus, the monitoring by a non-volatile memory controller; activating a zero bit counter for detecting a ratio of 1's to 0's on the data interface bus; and adjusting a threshold voltage (Vth), based on the ratio of the 1's to the 0's from the zero bit counter, by the non-volatile memory controller.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, a method includes, in response to a first signal received by the storage device, performing a soft power fail operation on a first section of the storage device. The soft power fail operation including: (1) signaling a power fail condition to a first plurality of controllers on the storage device, where the first plurality of controllers correspond to the first section of the storage device, (2) transferring data held in volatile memory of the storage device to non-volatile memory of the storage device, and (3) removing power from the first plurality of controllers.