Patents Assigned to SanDisk Technologies Inc.
  • Publication number: 20250254893
    Abstract: A non-volatile memory stack provides high bandwidth support to a specialized processor such as an AI processor. The high bandwidth flash (HBF) stack may be unitary, including all non-volatile memory together with a memory controller, or it may be hybrid, including a mixture of non-volatile and volatile memory together with a controller. The processor may be mounted on an interposer, and one or more of the HBF stacks and/or hybrid HBF stacks may then be mounted on the interposer alongside the processor.
    Type: Application
    Filed: October 31, 2024
    Publication date: August 7, 2025
    Applicant: Sandisk Technologies, Inc.
    Inventors: Nagesh Vodrahalli, Rama Shukla, Alper Ilkbahar, Chih Yang Li, Shrikar Bhagath
  • Patent number: 12379877
    Abstract: Instead of incorporating a single interface towards the host for transferring data, utilizing a designated write-only storage logging device. The write-only storage logging device can accept sequential streams and automatically overwrite. The controller will read the log material in a secure manner using a different and separate physical connection than the one used for write. The storage device may have LBA ranges that work as write-only as well as other LBA ranges, which are normal (both reads and writes are enabled). Both options will allow for a traditional file system as well as sharing the storage, but will still protect the log areas that would be used for events that should not be read out.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: August 5, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Julian Vlaiko, Judah Gamliel Hahn, Aki Bleyer, Shay Benisty, Alexander Bazarsky, Ariel Navon
  • Patent number: 12379878
    Abstract: Different pages of a quad-level cell (QLC) memory can have different data retention characteristics. A controller of a data storage device can store selected data in relatively-lower data retention pages of the QLC block. For example, data for an internal data storage device operation can be stored in the relatively-lower data retention pages of QLC memory, and host data can be stored in the relatively-higher data retention pages of QLC memory. Other examples are provided.
    Type: Grant
    Filed: June 4, 2024
    Date of Patent: August 5, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Meer Afroz Mohammed, Pawan Negi, Bhavadip Solanki
  • Patent number: 12379852
    Abstract: Rather than having unused die blocks, partial die blocks can contribute to a super block. In so doing, as much of the available physical capacity of the data storage device may be achieved. The result could be an increase in over provisioning (OP) and good capacity for the data storage device or an increase in die yield. An increase in good capacity through the use of previously unused physical blocks would lead to an increase in performance and endurance. A yield increase would result in a reduction in cost per die and per data storage device. A partial die block is the solution.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: August 5, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Alan D. Bennett, Sergey Anatolievich Gorobets
  • Patent number: 12379873
    Abstract: The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: August 5, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty, Rotem Sela
  • Patent number: 12380701
    Abstract: Systems, video cameras, and methods for predictive adjustment of multi-camera surveillance video data capture are described. A plurality of networked video camera is deployed with known spatial relationships and non-overlapping fields of view among cameras. When a video event is detected from video data for one of the video cameras, a video capture update message is selectively sent to other video cameras to modify their video capture operations. For example, an object detected by one camera may trigger adjustment of video capture operating parameters for cameras in a direction of travel of the object before it has entered the field of view of those other cameras.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: August 5, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Akhilesh Yadav, Ramanathan Muthiah
  • Patent number: 12373349
    Abstract: A Controller Memory Buffer (CMB) caching mechanism can be used for increased CMB performance. Rather than reading data and writing data from the static random access memory (SRAM), data is read from the SRAM. When data is read from the CMB in SRAM there is increase performance, but little space to process both read and write commands. Using a dynamic random access memory (DRAM) for write commands and CMB in SRAM for read commands allows for increased performance. Due to limited space in the SRAM, when the read commands are read from the host, the commands are deleted. This allows for relevant data stored in the SRAM to be used for the next command, but then deleted for the next command to be processed. The increase in performance is allowed, while not using extra SRAM or DRAM.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: July 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Stephen Gold, Judah Gamliel Hahn, Shay Benisty
  • Patent number: 12374403
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells retain a threshold voltage corresponding to data states. A control means applies a bit line voltage to the bit lines while determining whether the memory cells have the threshold voltage above one or more read levels associated with each of the data states in a first portion of a read operation. The control means groups the memory cells targeted for ones of the data states into data state groups based on the first portion of the read operation. The control means also supplies a near zero voltage to the bit lines coupled to the memory cells targeted for ones of the data states associated with at least one of the data state groups while reading the memory cells in subsequent portions of the read operation.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: July 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Panni Wang, Xiaojia Jia, Swaroop Kaza
  • Patent number: 12373113
    Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: July 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Daniel Joseph Linnen, Ariel Navon, Alexander Bazarsky, Ofir Pele
  • Patent number: 12373121
    Abstract: More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: July 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky, Judah Gamliel Hahn
  • Patent number: 12373358
    Abstract: The present disclosure generally relates to reducing link-up time between an upstream device and a downstream device. Rather than re-coordinating the link between devices each time, knowledge gained from a previous link-up is used to speed up the link-up. Typically, when both the upstream device and the downstream device have not changed, then the coefficient values for downstream port (DSP) transmission (Tx) equilibrium (EQ) that resulted in a desired bit error rate (BER) should not have changed either. Hence, rather than exchanging coefficients, the previous values can be reused with confidence eliminating the need to exchange coefficients. In so doing, the link-up process is much faster and system resources are not wasted on unnecessary coefficient exchanges.
    Type: Grant
    Filed: June 11, 2024
    Date of Patent: July 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventor: Shuli Shmaya
  • Patent number: 12374402
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in memory holes. The memory holes are arranged in rows comprising strings which are grouped into blocks comprising a first plane and a second plane. A control means is configured to program memory cells of the first plane and the second plane connected to one of the word lines using iterations of a program operation. The control means terminates programming of the first plane prior to completing programming of the first plane in response to determining the first plane programs slower than the second plane by a predetermined number of the iterations of the program operation. The control means adjusts the predetermined number of the iterations based on an additional verify iteration performed on at least some of the memory cells beyond the iterations of the program operation.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: July 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Dandan Yi, Xuan Tian, Liang Li, Vincent Yin
  • Patent number: 12368586
    Abstract: Aspects of a storage device are provided for managing a key version used for encryption and decryption and processing host commands associated with sanitized and non-sanitized logical pages using cryptographic erase. A controller of the storage device updates, in response to a sanitize command, a current address offset associated with the KV from a first address offset to a second address offset without changing the KV. In response to a subsequent read command, the controller determines whether the KV mismatches an expected KV obtained from the metadata beginning at the second address offset but matches or mismatches an expected KV obtained from the metadata beginning at the first address offset. The controller transmits garbage data decrypted using a different KV than the KV if a match, or an error message indicating a KV mismatch error if a mismatch. Thus, the controller may avoid returning garbage data for non-sanitized logical pages.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: July 22, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventor: Chaitanya Kavirayani
  • Patent number: 12366976
    Abstract: A storage device may maintain persistent data after converting from firmware associated with a first mode to firmware associated with a second mode. The device receives a firmware package associated with the second mode, determines when the package includes a descriptor, and executes a copy macro in the descriptor to translate a first data structure used in the first mode to the second data structure used in the second mode. When the device receives a commit command and determines that the second data structure is in a volatile memory, the device copies the second data structure to a non-volatile memory. After completing the commit command and power cycling, when the device is being formatted in the second mode, the device reads the second data structure from the non-volatile memory, transfers the second data structure to a persistence module, and formats in the second mode.
    Type: Grant
    Filed: June 11, 2024
    Date of Patent: July 22, 2025
    Assignee: Sandisk Technologies Inc.
    Inventors: Nagi Reddy Chodem, Naga Shankar Vadalamani, Navin Kochar
  • Patent number: 12367138
    Abstract: A storage device postpones entry into a read-only mode due to faulty blocks that cannot be written to on a memory device. The memory device is divided into blocks. Blocks used for storing host data are placed in a main area pool, blocks used for storing host data and for peak write operations are placed in a burst pool, and blocks used for storing control information are placed in the control pool. A controller executes a read-only mode extension protocol to determine when a number of faulty blocks in the main area pool, control pool, or burst pool is approaching a threshold for placing the storage device in a read-only mode. If the storage device is approaching the read-only mode, the controller reduces and/or repurposes a number of the blocks used for storing host data in the burst pool to prevent the storage device from entering the read-only mode phase.
    Type: Grant
    Filed: January 10, 2024
    Date of Patent: July 22, 2025
    Assignee: Sandisk Technologies Inc.
    Inventors: Karan Patel, Amit Chopra, Nitin Jain
  • Patent number: 12367931
    Abstract: Technology is disclosed herein for memory device with control circuitry having an efficient floorplan. Control circuitry resides in a control semiconductor die that is bonded to a memory die NAND strings extending in a z-direction. The memory die has bit lines extending across the NAND strings in an x-direction. First column control circuitry is connected to and configured to control a first set of bit lines. Second column control circuitry is connected to and configured to control a second set of bit lines. The second column control circuitry is stacked in an x-direction with the first column control circuitry. The control die also has system control circuitry configured to control the first column control circuitry and the second column control circuitry. The system control circuitry resides in the floorplan beside the stacked column control circuitry to allow for additional routing of electrical connections above the system control circuitry.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: July 22, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventor: Yuki Mizutani
  • Patent number: 12367940
    Abstract: Technology is disclosed herein for simultaneous lower tail program verify with upper tail verify. The memory system may apply a reference voltage to a word line following applying a program voltage to the word line. The memory system senses the first set of memory cells targeted for a first data state and the second set of memory cells targeted for a second data state. The memory system determines whether memory cells in the first set have a Vt greater than a maximum target Vt for the first data state based on the sensing of the first set of memory cells. The memory system also determines whether memory cells in the second set have a Vt less than a minimum target Vt for the second data state based on the sensing of the second set of memory cells.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: July 22, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Yingying Zhu, Chao Xu, Ming Wang, Liang Li
  • Patent number: 12366957
    Abstract: A host system includes an interface for coupling the host system to a data storage device. The host system also includes one or more processors, and memory storing one or more programs for execution by the one or more processors. The one or more programs include instructions for: determining if a retrim is needed for the data storage device; and in accordance with a determination that the retrim is needed: identifying a time to initiate a new trim on the data storage device; and causing the new trim on the data storage device at the time identified.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: July 22, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Eran Erez, Joseph R. Meza, Dylan B. Fairchild
  • Patent number: 12366977
    Abstract: Systems and methods are disclosed for providing host-independent data operations. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate a disk operation for the data storage device. In some embodiments, the controller can be configured to initiate a data operation, such as an authentication or data accessibility operation, a data security operation, etc., for example, in addition to or instead of a disk operation.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: July 22, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventor: Nitin Jain
  • Patent number: 12362007
    Abstract: Technology is disclosed for controlling reads in a memory device supporting different types of reads having different performance times (e.g., a relatively fast read such as a globally-referenced read and a slower read such as a self-referenced read). The data out latencies of the different read types may be different to accommodate the different performance times. The memory controller may mix the different types of reads. The memory controller tracks expected usage of the data bus and schedules read commands accordingly to avoid data collisions. A countdown timer may be used to track the earliest clock cycle at which the memory device may return data for a new read command to be issued. The memory controller may record what clock cycles the data bus is projected to be occupied with data and schedule read commands based on the projected data bus occupancy to avoid data collisions.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: July 15, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Rasmus Madsen, Lunkai Zhang, Martin Lueker-Boden