Patents Assigned to SanDisk Technologies LLC
  • Patent number: 10896690
    Abstract: A magnetic head includes a main pole configured to serve as a first electrode, an upper pole containing a trailing magnetic shield configured to a serve as a second electrode, and an electrically conductive portion located in a trailing gap between the main pole and the trailing magnetic shield. The electrically conductive portion is not part of a spin torque oscillator stack, and the electrically conductive portion includes at least one electrically conductive, non-magnetic material layer. The main pole and the trailing magnetic shield are electrically shorted by the electrically conductive portion across the trailing gap between the main pole and the trailing magnetic shield such that an electrically conductive path is present between the main pole and the trailing magnetic shield through the electrically conductive portion.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 19, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhigang Bai, Anna Zheng, Venkatesh Chembrolu, Supradeep Narayana, Yaguang Wei, Suping Song, Terence Lam, Michael Ho, Changqing Shi, Lijie Guan, Jian-Gang Zhu
  • Patent number: 10892267
    Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 12, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Kenji Sugiura, Hisakazu Otoi, Shigehisa Inoue, Yuki Fukuda
  • Patent number: 10892021
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: January 12, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Qui Nguyen, Arka Ganguly
  • Patent number: 10892279
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a gate dielectric located between the memory opening fill structures and the electrically conductive layers. Each of the memory opening fill structures includes a vertical semiconductor channel, a conductive core electrode, and a memory film located between the vertical semiconductor channel and the conductive core electrode. The memory film contains a layer stack including a first tunneling dielectric contacting the vertical semiconductor channel, a second tunneling dielectric contacting the conductive core electrode, and a charge storage layer located between the first tunneling dielectric and the second tunneling dielectric.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 12, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yukihiro Sakotsubo
  • Patent number: 10891974
    Abstract: A magnetic head includes a main pole configured to serve as a first electrode, an upper pole containing a trailing magnetic shield configured to a serve as a second electrode, and a record element located in a trailing gap between the main pole and the trailing magnetic shield. The record element includes an electrically conductive, non-magnetic material portion which is not part of a spin torque oscillator stack. The main pole and the trailing magnetic shield are electrically shorted by the record element across the trailing gap between the main pole and the trailing magnetic shield such that an electrically conductive path is present between the main pole and the trailing magnetic shield through the record element.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: January 12, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Venkatesh Chembrolu, Zhigang Bai, Yaguang Wei, Anna Zheng, Supradeep Narayana, Suping Song, Terence Lam, Michael Ho, Changqing Shi, Lijie Guan, Jian-Gang Zhu
  • Patent number: 10886459
    Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Young-Suk Choi, Won Ho Choi
  • Patent number: 10885994
    Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 10886458
    Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction for storing data may include a reference layer, a barrier layer, and a free layer. A barrier layer may be disposed between a reference layer and a free layer. A free layer may include a nucleation region and an arm. A nucleation region may be configured to form a magnetic domain wall. An arm may be narrower than a nucleation region and may extend from the nucleation region. An arm may include a plurality of pinning sites formed at predetermined locations along the arm for pinning a domain wall.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Young-Suk Choi, Won Ho Choi
  • Patent number: 10886366
    Abstract: A semiconductor structure includes a device region including field effect transistors located on a semiconductor substrate, and a planarization dielectric layer overlying the field effect transistors. A hydrogen-blocking structure can be formed to prevent subsequent hydrogen diffusion into the device region. A moat trench is formed through the planarization dielectric layer and into the semiconductor substrate around the device region. A ring-shaped hydrogen-diffusion-blocking material portion is formed within the moat trench. A horizontally-extending portion of a silicon nitride diffusion barrier layer is formed over the planarization dielectric layer. The ring-shaped hydrogen-diffusion-blocking material portion may include a vertically-extending annular portion of the silicon nitride layer, or may include an annular metal portion that is formed prior to formation of the silicon nitride diffusion barrier layer.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: January 5, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Noritaka Fukuo
  • Patent number: 10885984
    Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10886002
    Abstract: A method for detecting defects in a memory system includes receiving a command to perform a standard erase operation on at least one memory cell of the memory system. The method also includes performing a first defect detection operation on the at least one memory cell. The method also includes setting, in response to the first defect detection operation detecting a defect, a defect status indicator. The method also includes performing the standard erase operation on the at least one memory cell. The method also includes performing a second defect detection operation on the at least one memory cell. The method also includes setting, in response to the second defect detection operation detecting a defect, the defect status indicator.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Avinash Rajagiri, Yuvaraj Krishnamoorthy, Srikar Peesari, Ashish Ghai, Dongxiang Liao
  • Patent number: 10885991
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data rewrite operations. A non-volatile memory device comprises a non-volatile memory medium. A non-volatile memory device is configured to determine an error metric for a non-volatile memory medium in response to a read request for the non-volatile memory medium. A non-volatile memory device is configured to receive a refresh command from a controller over a bus. A non-volatile memory device is configured to rewrite data from a non-volatile memory medium during a predefined time period after receiving a refresh command in response to an error metric satisfying an error threshold.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Ward Parkinson, Martin Hassner, Nathan Franklin, Christopher Petti
  • Publication number: 20200410037
    Abstract: An apparatus performs vector matrix multiplication (VMM) for an analog neural network (ANN). The apparatus includes a column of NAND flash cells in series, where each NAND flash cell includes a control gate; a bit line connected to the column of NAND flash cells, where a current drawn from the NAND flash cells flows to the bit line; an integrator connected to the bit line; and a controller having programmed instructions to control the column of NAND flash cells by setting the voltage of the control gate of each NAND flash cell.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Federico Nardi, Gerrit Jan Hemink, Won Ho Choi
  • Publication number: 20200411066
    Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 31, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
  • Publication number: 20200411065
    Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.
    Type: Application
    Filed: July 2, 2019
    Publication date: December 31, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
  • Publication number: 20200411589
    Abstract: A memory array is provided that includes a first memory level having a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element, and a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells.
    Type: Application
    Filed: July 2, 2019
    Publication date: December 31, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Lei Wan, Tsai-Wei Wu, Jordan A. Katine
  • Publication number: 20200411109
    Abstract: A partial page sensing method and system are provided in which, while a bit line voltage (VBLC) is applied to first bit lines of a first partial page of a memory cell array, second bit lines, of a second partial page are floated. The second bit lines of the second partial page are bit lines which are interleaved with the first bit lines of the first partial page. Bit lines associated with one or more additional partial pages may be grounded or floated. A bit line associated with an additional partial page which is adjacent to one of the first bit lines may be floated.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Yu-Chung Lien
  • Publication number: 20200411112
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Publication number: 20200411100
    Abstract: Methods for improving read time performance and energy consumption when reading multiple pages within a memory block by dynamically skipping or accelerating unselected word line discharge cycles are described. In some cases, a controller or one or more control circuits in communication with word lines and bit lines associated with a memory block may detect that a read command or instruction for reading a second page within the memory block has arrived prior to the word line discharge phase associated with reading a first page within the memory block, and in response, the controller may skip the discharge cycle for unselected word lines within the memory block prior to reading the second page and initiate the next page read for the second page after a partial discharge period of time.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 31, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Norihiro Kamae, Yosuke Kato
  • Publication number: 20200413531
    Abstract: To protect memory cards, such as SD type cards, and similar devices from Electrostatic Discharge (ESD), the input pads of the device include points along their edges that are aligned with correspond points on a conductive frame structure mounted adjacent the input pad to form a spark gap. The input pads are connected to a memory controller or other ASIC over signal lines that include a diode located between the input pad and the ASIC and a resistance located between the input pad and the diode. The resistance and diode are selected such that an ESD event at an input pad triggers a discharge across the spark gap before it is transmitted on to the ASIC, while also allowing a high data rate for signals along the signal line.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Albert Wallash, Shajith Musaliar Sirajudeen, John Thomas Contreras