Abstract: A memory system is described having an x-direction (bit line direction) divided sub-block mode. Each block is divided in a y-direction and in the x-direction into a number of groups of contiguous NAND strings that are referred to as XY sub-blocks. The memory system performs a memory operation in parallel in multiple XY sub-blocks in a block while inhibiting the memory operation in the other XY sub-blocks in the block. Each XY sub-block for which the memory operation is performed has its NAND strings connected to a different set of contiguous bit lines. In an aspect the memory operation is a program operation with selected memory cells in each of the multiple XY sub-blocks programmed in parallel while inhibiting programming of all memory cells in all other XY sub-blocks in the block. In one aspect, the memory operation is an erase operation.

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes each comprising a channel. The memory cells retain a threshold voltage and are operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is configured to apply a predetermined refresh read voltage to the word lines at predetermined intervals of time during a refresh read operation to maintain the memory cells in the second read condition. The control means also adjusts a read setup time in which the word lines are ramped up and the channel is discharged during a read operation based on occurrences of the refresh read operation.

Abstract: Technology is disclosed herein for a memory device having a narrow gap between planes and a method of shrinking the gap between planes. A first and second adjacent planes each has a word line (WL) hookup region at mid-plane. A dummy array region resides between the two planes. The dummy array region may contain a stack of alternating layers of a first insulating material and a second insulating material. There is a first electrical isolation structure between the dummy array region and a stack in the first plane. There is a second electrical isolation structure between the dummy array region and a stack in a second plane. The electrical isolation structures may be formed in narrow trenches. The combination of the dummy array region and the two electrical isolation structures results in a very short gap between the adjacent planes.

Abstract: The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

Abstract: A non-volatile memory system programs memory cells from an erased threshold voltage distribution to programmed threshold voltage distributions by performing hole pre-charging of channels of unselected NAND strings in a selected block of a selected plane including applying a source voltage to a selected signal line of a plurality of signal lines that are isolated from each other. The selected signal line is positioned between the selected block and an unselected block and is connected to a selected source line of a plurality of source lines that are isolated from each other. The selected source line is connected to the selected block. The source voltage is greater in magnitude than any predetermined threshold voltage of the erased threshold voltage distribution. After the pre-charging, the system boosts channels of unselected NAND strings in the selected block and applies a program voltage to selected NAND strings in the selected block.

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

Abstract: The present disclosure is related to a programming technique for a memory device that includes a plurality of memory cells arranged in a plurality of word lines. An operating temperature of the memory device is determined. A spike pre-charge voltage is selected based on the operating temperature of the memory device. A first word line and a second word line are programmed in a first programming pass of a multi-pass programming operation. After the first programming pass is completed on the first and second word lines, the first word line is further programmed in a second programming pass that includes a plurality of program loops with pre-charge operations. The spike pre-charge voltage is applied to the second word line during each pre-charge operation.

Abstract: A storage device is disclosed herein. The storage device comprises a non-volatile memory, where the non-volatile memory includes a block of 3N wordlines partitioned into a plurality of sub-blocks. The plurality of sub-blocks include an upper sub-block of a first subset of the block of 3N wordlines, a lower sub-block of a second subset of the block of 3N wordlines, and a middle sub-block of a third subset of the block of 3N wordlines. Further, the storage device comprises control circuitry coupled to the block of 3N wordlines and configured to: perform a program operation in a normal order programming sequence on the upper sub-block; perform a program operation in a reverse order programming sequence on the lower sub-block; and perform a program operation in the reverse order programming sequence on the middle sub-block.

Abstract: Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.

Abstract: Technology is disclosed herein for a memory system that includes one or more control circuits configured to connect to a three-dimensional memory structure that includes word lines, with each word line connected to a word line driver at one end. The one or more control circuits are configured to, in a program verify operation, sense memory cells of a first region of a selected word line for a first sense time and sense memory cells of a second region of the selected word line for a second sense time while applying a program-verify voltage to the selected word line. The first region is closer to the word line driver than the second region.

Abstract: An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches and the second plurality of data latches.

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

Abstract: A method for multi-state programming of a non-volatile memory structure, comprising: (1) initiating a programming operation with respect to multiple program states, (2) applying, to all selected word lines of the memory structure, a programming voltage bias (VPGM) level pre-determined to be suitable for programming a highest program state of the multiple program states, wherein the programming voltage bias level is applied according to a given program pulse width, and (3) with respect to each program state other than the highest program state of the multiple program states, applying a zero-volt bitline voltage bias (VBL) to one or more bitlines that are associated with one or more memory elements to be programmed to the program state, wherein the zero-volt bitline voltage bias is applied according to a respective program sub-pulse width that is less than the given program pulse width.

Abstract: Technology is disclosed herein for reading programmable resistance memory cells. A first (faster) self-referenced read (SRR) of a group of memory cells is performed and if successful the read is complete. However, if the first SRR fails then a second (slower or nominal) SRR is performed. The bit error rate (BER) of the second SRR may be significantly lower than the BER of the first SRR. However, the BER of the first SRR may be low enough such that most of the time the first SRR is successful. Therefore, most of the time the read is completed with just the first SRR, thereby providing for an SRR having on average is faster than if just the second SRR had been used. Moreover, the effective BER of the SRR is extremely low due to the low BER of the second SRR.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to identify at least one grouping of the memory cells to be programmed with a multi-pass programming operation. The control means is also configured to program the at least one grouping of the memory cells using the multi-pass programming operation. The control means is additionally configured to program the memory cells other than the at least one grouping of the memory cells in a full sequence programming operation.

Abstract: A non-volatile storage apparatus includes non-volatile memory cells, word lines connected to the non-volatile memory cells, and a control circuit connected to the word lines and the memory cells. The word lines include data word lines and dummy word lines. Memory cells connected to data word lines are configured to store host data. Memory cells connected to dummy word lines do not store host data. The control circuit is configured to erase, program and read the memory cells. Errors from threshold voltage up-shifting in the memory cells connected to dummy word lines is prevented by adjusting the voltage applied to dummy word lines.

Abstract: An apparatus is provided that includes a block of memory cells, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a count of a number of times that the block of memory cells previously has been programmed and erased, determining an erase voltage based on the count, and applying an erase pulse having the erase voltage to the block of memory cells.

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.