Abstract: Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.

Abstract: Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is referred to herein as a “separate bit line architecture”. The separate bit line architecture allows the control semiconductor die to control a memory operation in parallel in the two memory semiconductor dies. Moreover, the separate bit line architecture allows for good scaling of a memory device with multiple dies bonded together.

Abstract: To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word line needing a dummy positioning operation. The control means is also configured to program the memory cells connected to the dummy word line to adjust the threshold voltage to a predetermined position threshold voltage in the dummy positioning operation in response to determining the one of the plurality of word lines being programmed in the program operation is the particular one of the word lines.

Abstract: A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at least one memory cell of the selected word line to a last data state in at least one last data state programming loop. In response to both the total number of programming loops being less than a first predetermined threshold and the number of last data state programming loops being equal to a second predetermined threshold, the control circuitry automatically skips verify in a final programming loop.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to program and verify the memory cells during a program operation. The memory cells associated with predetermined ones of the data states are not verified until the memory cells associated with specific prior ones of the data states finish programming to define verify windows ranging between each one of the specific prior ones of the data states and each one of the predetermined ones. The control means adjusts the verify windows in response to the memory cells associated with one of the specific prior ones of the data states not finishing programming before the one of the predetermined ones of the at least one of the verify windows is verified.

Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks; and control circuitry coupled to the N wordlines. The control circuitry is configured to: determine a program status of an unselected sub-block of the plurality of sub-blocks before performing an operation on a selected sub-block of the plurality of sub-blocks; based on determining that the program status of the unselected sub-block is programmed, perform a precharge operation including applying a first precharge time; and based on determining that the program status of the unselected sub-block is not programmed, perform a precharge operation including applying a second precharge time, wherein the first precharge time is for a longer period than the second precharge time.

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Abstract: The memory device has a plurality of memory blocks including a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry that is in communication with the plurality of memory blocks. The control circuitry is configured to receive a data write instruction. The control circuitry is further configured to program the memory cells of the memory blocks to an SLC format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry is configured to program the memory cells of at least some of the plurality of memory blocks from the SLC format to a TLC format.

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of a first one and a second one of the plurality of strings to a predetermined one of a plurality of data states in a first program operation. The control means then selects both the first one and the second one of the plurality of strings together and programs the memory cells of the full circle rows together in a second program operation.

Abstract: The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.

Abstract: Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the second block while compensating for a difference in resistance of the first and second electrical pathways. In one aspect, the control circuit discharges a first sense node for a different period of time than a second sense node to compensate for the difference in resistance. Compensating for the difference in resistance compensates for a different IR drop of the electrical pathways.

Abstract: A non-volatile memory system is configured to program non-volatile memory cells by applying doses of programming to the memory cells and performing a program-verify operation following each dose of programming. Each dose of programming and the corresponding program-verify operation following the dose of programming is referred to as a program loop. The program-verify operation comprises applying a verify reference voltage to a selected word line and applying an overdrive voltage to unselected word lines. To reduce the amount of current used, the memory system includes a loop dependent reduction in the ramp-up rate of the overdrive voltage applied to unselected word lines during program-verify.

Abstract: A memory system programs memory cells connected to a selected word line by applying doses of programming and performing program-verify between doses. An efficient and low current program-verify operation includes: while scanning the results of a previous program-verify operation, ramp up voltages on the select lines for the next program-verify operation without waiting for the scan to complete and ramp up voltages on unselected word lines for the next program-verify operation following a step signal (so that voltage applied to the unselected word lines rise in steps) without waiting for the scan to complete.

Abstract: A non-volatile memory system detects a memory operation failure. In response to the memory operation failure, the system determines whether adjusting an overdrive voltage applied to a word line avoids the memory operation failure. If adjusting the overdrive voltage applied to the word line avoids the memory operation failure, then future memory operations are performed by applying the adjusted overdrive voltage to the word line.

Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to receive a read command directed to at least one logical page of data during a program operation to store the at least one logical page of data in a plurality of non-volatile memory cells. The control circuits are further configured to stop the program operation at an intermediate stage of programming, read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page and obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

Abstract: The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes three possible data states. Prior to the second pass, the control circuitry is configured to read the foggy data and the parity data and reconstruct the final data from the foggy data and the parity data. In the second pass, the control circuitry is configured to program the memory cells of the selected word line from the foggy data to the final data.

Abstract: A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.