Patents Assigned to SanDisk Technologies LLC
  • Publication number: 20230282295
    Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a magnitude of a boosting voltage bias (VPASS) that is to be applied to an unselected word line may be determined according to the determined total number of erase/programming (EP) cycles.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Xue Bai Pitner, Ken Oowada
  • Publication number: 20230282288
    Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line. During some read operations, this allows the memory device to operate with lower power requirements.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 7, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Ohwon Kwon, James Kai, Yuki Mizutani
  • Publication number: 20230274785
    Abstract: A non-volatile semiconductor memory device comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.
    Type: Application
    Filed: February 28, 2022
    Publication date: August 31, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Sujjatul Islam, Yu-Chung Lien, Ravi Kumar, Xue Pitner
  • Publication number: 20230268015
    Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including smart verify loops. The control means discards the smart verify programming voltage and determines another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the strings in response to a quantity of the smart verify loops needed to complete programming of the memory cells associated with the first one of the strings being outside a predetermined threshold criteria.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Ke Zhang, Minna Li, Liang Li
  • Publication number: 20230267981
    Abstract: Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 24, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Ward Parkinson, James O'Toole, Thomas Trent, Nathan Franklin, Michael Grobis, James W. Reiner, Hans Jurgen Richter, Michael Nicolas Albert Tran
  • Publication number: 20230268013
    Abstract: A non-volatile storage apparatus that comprises a plurality of planes of non-volatile memory cells is capable of concurrently programming memory cells in multiple planes. In order to screen for failure of the programming process in a subset of planes, the completion of programming of a fastest plane to a particular data state is used as a trigger to test for program failure of other planes to a different data state. In one embodiment, the test for program failure of other planes to the different data state comprises determining if the memory cells of the other planes that are targeted for programming to the different data state have successfully completed verification of programming for the different data state. The programming process is stopped for those planes that fail the test.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 24, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Shota Murai, Hideto Tomiie
  • Patent number: 11735288
    Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: August 22, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Hua-Ling Cynthia Hsu, YenLung Li
  • Publication number: 20230260589
    Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Hua-Ling Cynthia Hsu, YenLung Li
  • Publication number: 20230259300
    Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Hua-Ling Cynthia Hsu, Aaron Lee
  • Publication number: 20230259149
    Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: James O'Toole, Ward Parkinson, Thomas Trent
  • Publication number: 20230260582
    Abstract: When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Jayavel Pachamuthu, Dana Lee
  • Publication number: 20230253049
    Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 10, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Deepanshu Dutta, Sarath Puthenthermadam, Jiahui Yuan
  • Publication number: 20230253047
    Abstract: A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.
    Type: Application
    Filed: February 7, 2022
    Publication date: August 10, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xue Pitner, Yu-Chung Lien, Sarath Puthenthermadam, Sujjatul Islam
  • Publication number: 20230253056
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including a dummy word line and other data word lines. The memory cells are disposed in memory holes and configured to retain a threshold voltage. A control means is coupled to the word lines and the memory holes and is configured to determine whether one of the word lines being programmed in a program operation is a particular one of the word lines adjacent the dummy word line needing a dummy positioning operation. The control means is also configured to program the memory cells connected to the dummy word line to adjust the threshold voltage to a predetermined position threshold voltage in the dummy positioning operation in response to determining the one of the plurality of word lines being programmed in the program operation is the particular one of the word lines.
    Type: Application
    Filed: February 4, 2022
    Publication date: August 10, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Abhijith Prakash
  • Publication number: 20230253046
    Abstract: The memory device includes a plurality of dies, and each die includes a plurality of blocks with a plurality of word lines. Some of the word lines are arranged in a plurality of exclusive OR (XOR) sets with each XOR set containing word lines in the same positions across the plurality of dies. The memory device further includes a controller that is configured to program the word lines of the blocks of at least one of the dies in a first programming direction. The controller is further configured to program the word lines of the blocks of at least one other die in a second programming direction that is opposite of the first programming direction.
    Type: Application
    Filed: February 4, 2022
    Publication date: August 10, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Qing Li, Henry Chin, Xiaoyu Yang
  • Publication number: 20230253053
    Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings. The memory cells are configured to retain a threshold voltage. The rows include full circle rows and semi-circle rows in which the memory holes are partially cut by a slit half etch. The memory holes of the semi-circle rows are coupled semi-circle bit lines and the memory holes of the full circle rows are coupled to full circle bit lines. A control means is configured to erase the memory cells in an erase operation. During the erase operation, the control means creates a capacitive coupling between each of the semi-circle bit lines and at least one neighboring one of the full circle bit lines to increase a semi-circle erase voltage applied to each of the semi-circle bit lines.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 10, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Kou Tei, Ohwon Kwon
  • Publication number: 20230253048
    Abstract: The memory device includes an array of memory cells, which are configured to retain multiple bits per memory cell, arranged in a plurality of word lines. A controller is configured to program the memory cells of a selected word line in a first programming pass. The first programming pass includes a plurality of programming pulses, each including the application of a programming voltage Vpgm by the controller to a control gate of the selected word line for a first duration. The controller is also configured to further program the memory cells of the selected word line in a second programming pass. The second programming pass includes a plurality of programming pulses, each of which includes the application of a programming voltage Vpgm by the controller to the control gate of the selected word line for a second duration that is different than the first duration.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 10, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Sujjatul Islam, Ravi Kumar
  • Patent number: 11721397
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 8, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Jianzhi Wu, Jia Li, Yanjie Wang
  • Publication number: 20230238062
    Abstract: The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines, which are arranged in sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller reads data of the edge one word lines of the unselected sub-blocks adjacent the selected sub-block and stores this data in a temporary location external of the block before erasing the memory cells of the selected sub-block. The controller then re-programs the data that is being temporarily stored back into the memory cells of the edge word lines of the unselected sub-blocks after erase of the selected sub-block is completed.
    Type: Application
    Filed: January 25, 2022
    Publication date: July 27, 2023
    Applicant: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Patent number: 11705206
    Abstract: Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: July 18, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Abu Naser Zainuddin, Jia Li, Jiahui Yuan, Bo Lei