Patents Assigned to SanDisk Technologies LLC
  • THREE-BIT-PER-CELL PROGRAMMING USING A FOUR-BIT-PER-CELL PROGRAMMING ALGORITHM
    Publication number: 20230410921
    Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Jiacen Guo, Takayuki Inoue, Hua-Ling Hsu
  • TEMPERATURE-DEPENDENT WORD LINE VOLTAGE AND DISCHARGE RATE FOR REFRESH READ OF NON-VOLATILE MEMORY
    Publication number: 20230410901
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.
    Type: Application
    Filed: May 24, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Dong-Il Moon, Abhijith Prakash, Wei Zhao, Henry Chin
  • Three-dimensional memory device with a columnar memory opening arrangement and method of making thereof
    Patent number: 11849578
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a plurality of periodic two-dimensional arrays of memory openings vertically extending through the alternating stack, a plurality of periodic two-dimensional arrays of memory opening fill structures, and bit lines. The bit lines laterally extend along a second horizontal direction. Each periodic two-dimensional array of memory openings includes a plurality of columns of memory openings in which neighboring columns of memory openings are laterally spaced apart along a first horizontal direction with an intercolumnar pitch. Memory openings within each column of memory openings are laterally spaced apart along the second horizontal direction with a nearest-neighbor pitch.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 19, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Tatsuya Inoue
  • Techniques for erasing the memory cells of edge word lines
    Patent number: 11848059
    Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: December 19, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Jiacen Guo, Xiang Yang, Abhijith Prakash
  • ARRAY DEPENDENT VOLTAGE COMPENSATION IN A MEMORY DEVICE
    Publication number: 20230402099
    Abstract: The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Ke Zhang, Liang Li, Ming Wang
  • STATE LOOK AHEAD QUICK PASS WRITE ALGORITHM TO TIGHTEN ONGOING NATURAL THRESHOLD VOLTAGE OF UPCOMING STATES FOR PROGRAM TIME REDUCTION
    Publication number: 20230402110
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Ke Zhang, Ming Wang, Liang Li
  • HIGH SPEED TOGGLE MODE TRANSMITTER WITH CAPACITIVE BOOSTING
    Publication number: 20230402107
    Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Nitin Gupta, Shiv Harit Mathur, Ramakrishnan Subramanian, Dmitry Vaysman
  • READ TECHNIQUES TO REDUCE READ ERRORS IN A MEMORY DEVICE
    Publication number: 20230402105
    Abstract: The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which are located on an opposite side of the word line from the voltage driver. The control circuitry reads the memory cells of the first group using a first read mode and reads the memory cells of the second group using a second read mode that is different than the first read mode to reduce a fail bit count during read.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Jiacen Guo, Xiang Yang
  • Three-dimensional memory device with backside support pillar structures and methods of forming the same
    Patent number: 11844222
    Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: December 12, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shunsuke Takuma, Yuji Totoki, Seiji Shimabukuro, Tatsuya Hinoue, Kengo Kajiwara, Akihiro Tobioka
  • Systems and methods for dynamically sensing a memory block
    Patent number: 11842775
    Abstract: A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and increase efficiency.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: December 12, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Nidhi Agrawal, Bo Lei, Zhenni Wan
  • NON-VOLATILE MEMORY WITH TUNING OF ERASE PROCESS
    Publication number: 20230395157
    Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Jiahui Yuan, Yanjie Wang
  • Smart erase verify in non-volatile memory structures
    Patent number: 11837297
    Abstract: A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase cycle is complete, a determination is made as to whether the stored erase/verify loop count equals a pre-defined threshold count. Further, if the stored count does not equal the pre-defined threshold count, the initial stored erase voltage level is adjusted such that, upon applying the adjusted erase voltage level in a subsequent erase cycle, an erase/verify loop count will now equal the pre-defined threshold count.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: December 5, 2023
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Transistor circuits including fringeless transistors and method of making the same
    Patent number: 11837601
    Abstract: A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 5, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jun Akaiwa, Dai Iwata, Hiroshi Nakatsuji, Eiichi Fujikura, Hiroyuki Ogawa
  • Non-volatile memory with adjusted bit line voltage during verify
    Patent number: 11837296
    Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: December 5, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Jiahui Yuan, Ohwon Kwon
  • Transistors with stepped contact via structures and methods of forming the same
    Patent number: 11837640
    Abstract: A transistor includes a semiconductor substrate including a first active region, a second active region, and a semiconductor channel, a gate stack structure that overlies the semiconductor channel, a proximal dielectric material layer overlying the semiconductor substrate, laterally surrounding the gate stack structure, a distal dielectric material layer overlying the proximal dielectric material layer, and a first contact via structure contacting the first active region having a greater lateral extent at a level of the proximal dielectric material layer than at a level of the distal dielectric material layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 5, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuhiro Togo, Hiroshi Nakatsuji
  • LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES
    Publication number: 20230386569
    Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Muhammad Masuduzzaman, Jiacen Guo
  • NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT
    Publication number: 20230386585
    Abstract: To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are lowered to respective intermediate voltages while lowering the voltage on the selected word line in order to achieve a channel potential gradient in the floated NAND strings of the unselected sub-blocks that does not result in read disturb. Subsequently, the selected word line is raised to the appropriate read compare voltage so the selected memory cells can be sensed.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Jiacen Guo, Xiang Yang, Xiaochen Zhu
  • CROSS-POINT ARRAY REFRESH SCHEME
    Publication number: 20230386543
    Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Michael Nicolas Albert Tran, Michael K. Grobis, Ward Parkinson, Nathan Franklin
  • METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING
    Publication number: 20230386580
    Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Peng Wang, Jia Li, Behrang Bagheri, Keyur Payak, Bo Lei, Long Pham, Jun Wan
  • HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES
    Publication number: 20230386568
    Abstract: A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Muhammad Masuduzzaman, Jiacen Guo