Patents Assigned to SanDisk Technologies LLC
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Publication number: 20230410921Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.Type: ApplicationFiled: June 21, 2022Publication date: December 21, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Deepanshu Dutta, Jiacen Guo, Takayuki Inoue, Hua-Ling Hsu
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Patent number: 11848059Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.Type: GrantFiled: November 18, 2021Date of Patent: December 19, 2023Assignee: SanDisk Technologies LLCInventors: Jiacen Guo, Xiang Yang, Abhijith Prakash
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Publication number: 20230402099Abstract: The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Applicant: SanDisk Technologies LLCInventors: Ke Zhang, Liang Li, Ming Wang
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Publication number: 20230402110Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in strings and are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages associated with the data states targeted for each of the memory cells being programmed during verify loops of a program-verify operation. The control means slows the memory cells targeted for a selected one of the data states identified as being faster to program than other ones of the memory cells during one of verify loops associated with an earlier one of data states.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Applicant: SanDisk Technologies LLCInventors: Ke Zhang, Ming Wang, Liang Li
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Publication number: 20230402107Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Applicant: SanDisk Technologies LLCInventors: Nitin Gupta, Shiv Harit Mathur, Ramakrishnan Subramanian, Dmitry Vaysman
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Publication number: 20230402105Abstract: The memory device includes a memory block with a plurality of memory cells, which are programmed to multiple bits per memory cell, arranged in a plurality of word lines. Control circuitry is provided and is configured to read the memory cells of a selected word line. The control circuitry separates the memory cells of the selected word line into a first group of memory cells, which are located on a side of the word line are near a voltage driver, and a second group of memory cells, which are located on an opposite side of the word line from the voltage driver. The control circuitry reads the memory cells of the first group using a first read mode and reads the memory cells of the second group using a second read mode that is different than the first read mode to reduce a fail bit count during read.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Applicant: SanDisk Technologies LLCInventors: Jiacen Guo, Xiang Yang
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Patent number: 11842775Abstract: A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and increase efficiency.Type: GrantFiled: October 21, 2021Date of Patent: December 12, 2023Assignee: SanDisk Technologies LLCInventors: Nidhi Agrawal, Bo Lei, Zhenni Wan
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Publication number: 20230395157Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.Type: ApplicationFiled: June 3, 2022Publication date: December 7, 2023Applicant: SanDisk Technologies LLCInventors: Yi Song, Jiahui Yuan, Yanjie Wang
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Patent number: 11837296Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.Type: GrantFiled: October 19, 2021Date of Patent: December 5, 2023Assignee: SanDisk Technologies LLCInventors: Yu-Chung Lien, Jiahui Yuan, Ohwon Kwon
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Patent number: 11837297Abstract: A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase cycle is complete, a determination is made as to whether the stored erase/verify loop count equals a pre-defined threshold count. Further, if the stored count does not equal the pre-defined threshold count, the initial stored erase voltage level is adjusted such that, upon applying the adjusted erase voltage level in a subsequent erase cycle, an erase/verify loop count will now equal the pre-defined threshold count.Type: GrantFiled: June 10, 2021Date of Patent: December 5, 2023Assignee: SanDisk Technologies LLCInventor: Xiang Yang
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Publication number: 20230386568Abstract: A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Deepanshu Dutta, Muhammad Masuduzzaman, Jiacen Guo
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Publication number: 20230386586Abstract: The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a maximum number of program loops. The maximum number of program loops is dependent on the temperature that is detected.Type: ApplicationFiled: May 27, 2022Publication date: November 30, 2023Applicant: SanDisk Technologies LLCInventors: Sujjatul Islam, Ravi Kumar
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Publication number: 20230386585Abstract: To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are lowered to respective intermediate voltages while lowering the voltage on the selected word line in order to achieve a channel potential gradient in the floated NAND strings of the unselected sub-blocks that does not result in read disturb. Subsequently, the selected word line is raised to the appropriate read compare voltage so the selected memory cells can be sensed.Type: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Applicant: SanDisk Technologies LLCInventors: Jiacen Guo, Xiang Yang, Xiaochen Zhu
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Publication number: 20230386569Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Muhammad Masuduzzaman, Jiacen Guo
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Publication number: 20230386580Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: SanDisk Technologies LLCInventors: Peng Wang, Jia Li, Behrang Bagheri, Keyur Payak, Bo Lei, Long Pham, Jun Wan
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Publication number: 20230386543Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Michael K. Grobis, Ward Parkinson, Nathan Franklin
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Patent number: 11829281Abstract: Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.Type: GrantFiled: June 16, 2021Date of Patent: November 28, 2023Assignee: SanDisk Technologies LLCInventors: Jang Woo Lee, Srinivas Rajendra, Anil Pai, Venkatesh Ramachandra
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Patent number: 11830564Abstract: Apparatuses and techniques are presented for detecting bit line open circuits and short circuits in a memory device in which a memory die is inverted and bonded to a control die. In one approach, the control die comprises a set of bit lines which are connected to a set of bit lines of the memory die, and the set of bit lines of the control die comprise ground transistors, e.g., transistors connected to a ground node. Ground transistors of even-numbered bit lines may be commonly controlled, while ground transistors of odd-numbered bit lines are commonly controlled. The ground transistors may be controlled to detect open circuits and short circuits in the bit lines of the control die and the memory die. A laser scanning technique can also be used to determine a physical location of a defect of a bit line.Type: GrantFiled: August 30, 2021Date of Patent: November 28, 2023Assignee: SanDisk Technologies LLCInventor: Brian Murphy
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Publication number: 20230377643Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.Type: ApplicationFiled: May 23, 2022Publication date: November 23, 2023Applicant: SanDisk Technologies LLCInventors: Huiwen Xu, Jun Wan, Bo Lei
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Publication number: 20230377655Abstract: The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Applicant: SanDisk Technologies LLCInventors: Huiwen Xu, Nidhi Agrawal, Zhenni Wan, Bo Lei, Jun Wan
