Abstract: A non-volatile memory apparatus comprises a stack of integrated memory assemblies. Each integrated memory assembly includes a memory die bonded to a control die and a set of power pads connected to metal lines in the respective memory die and control die. The memory dies comprise a non-volatile memory structure and a top metal layer for transmitting power signals above the memory structure. The control dies comprise a substrate, a control circuit positioned on the substrate for performing memory operations on a corresponding memory structure and a set of metals layers above the control circuit. The substrate comprises a set of conductive vias through the substrate that connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit for routing signals between integrated memory assemblies.

Abstract: The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a maximum number of program loops. The maximum number of program loops is dependent on the temperature that is detected.

Abstract: Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.

Abstract: Apparatuses and techniques are presented for detecting bit line open circuits and short circuits in a memory device in which a memory die is inverted and bonded to a control die. In one approach, the control die comprises a set of bit lines which are connected to a set of bit lines of the memory die, and the set of bit lines of the control die comprise ground transistors, e.g., transistors connected to a ground node. Ground transistors of even-numbered bit lines may be commonly controlled, while ground transistors of odd-numbered bit lines are commonly controlled. The ground transistors may be controlled to detect open circuits and short circuits in the bit lines of the control die and the memory die. A laser scanning technique can also be used to determine a physical location of a defect of a bit line.

Abstract: The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.

Abstract: A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data state of the first word line exceeds the critical voltage by a threshold. In response to the upper tail of the erased data state exceeding the critical voltage by the threshold, the controller then alternates between the first and second programming passes until the first programming pass is completed on the remaining word lines of the memory block.

Abstract: A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD transistors. With the at least one first unselected partial SGD transistor electrically floating, the method continues with reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect.

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.

Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

Abstract: A method of operating a non-volatile semiconductor memory device is disclosed. The method comprises: during a first pre-read cycle of a read operation, ramping up a control signal on a wordline selected for the read operation to a first target pre-read voltage and ramping up a control signal on a drain-side select (SGD) transistor of an unselected string of the plurality of strings to a second target pre-read voltage. The method further comprises during a second pre-read cycle of the read operation, ramping down the control signal on the wordline to a target read voltage and ramping down the control signal on the SGD transistor of the unselected string to a third target pre-read voltage after a delay period after the triggering edge of the second pre-read cycle.

Abstract: The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.

Abstract: Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle clock in the current regulation mode. The memory system determines a target duty cycle for the random duty cycle clock that will regulate the input current of the charge pump to a target current, given the present output voltage. A clock based on the random duty cycle clock is provided to a clock input of the charge pump to regulate the charge pump current.

Abstract: The memory device includes a controller that is configured to program a plurality of memory cells of a selected word line in a plurality of programming loops and count the number of programming loops to complete programming. The controller is also configured to compare the number of programming loops to complete programming of the memory cells of the selected word line to at least one of a predetermined upper limit and a predetermined lower limit to determine if a plane containing the selected word line is at an elevated risk for read failure. In response to the controller making a determination that the plane containing the selected word line is at an elevated risk for read failure, the controller is configured to conduct a post write read operation at least one word line of the plurality of word lines.

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

Abstract: The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N?1. The data state N?1 has a lower voltage threshold than the data state N.

Abstract: To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

Abstract: A hybrid charge pump is disclosed that employs novel arrangements of depletion-mode n-channel semiconductor devices and enhancement-mode p-channel semiconductor devices that eliminate or otherwise substantially reduce voltage drops that would otherwise occur across semiconductor device arrangements in existing charge pumps. As a result, the hybrid charge pump disclosed herein achieves the same output voltages as conventional charge pumps while requiring a reduced physical die area. Additionally, a hybrid charge pump arrangement disclosed herein employs a novel clocking scheme that reduces or eliminates reverse currents in the hybrid charge pump arrangement.

Abstract: When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, a laterally perforated support pillar structure vertically extending through the alternating stack and the retro-stepped dielectric material portion, and a layer contact via structure laterally surrounded by the laterally perforated support pillar structure and contacting a top surface of a topmost electrically conductive layer within an area of the laterally perforated support pillar structure. Each electrically conductive layer within the area of the laterally perforated support pillar structure extends through the lateral openings.