Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a dummy memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the dummy memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the dummy memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: Embodiments are disclosed relating to garbage collecting storage blocks in a storage device. In one embodiment, data is selected for relocation from a storage block in a storage device during reclaiming of the storage block. The data may be selected based on metadata that identifies whether data is valid at a time when the reclaiming is initiated. In some embodiments, prior to relocating data from the storage block, the metadata is captured from a data structure that identifies whether data on the storage device is valid. In one embodiment, a determination of whether the selected data has become invalid due to other data that is stored during the reclaiming is made. In some embodiments, in response to determining that the selected data has become invalid, the selected data is specified as invalid in the data structure.

Abstract: In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks.

Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.

Abstract: A method is provided that includes forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction, forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor including a second sidewall gate disposed in the first direction, and forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber including an air gap.

Abstract: The amount of remapping data in a file system of a memory device is reduced. In one aspect, for each request access, e.g., read or write operation, the memory cells of a primary physical address are evaluated. If the evaluation indicates the memory cells are good, the read or write operation proceeds. If the memory cells have a failure such as uncorrectable errors, the primary physical address is hashed to obtain an auxiliary physical address. If the auxiliary physical address is not available, the primary physical address can be hashed again to obtain another auxiliary physical address. In another aspect, per-page remapping is performed until a threshold number of bad pages in a block are detected, after which the entire block is remapped. In another aspect, pages of a block are remapped to auxiliary pages based on a block identifier.

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

Abstract: A device or apparatus may be configured to perform memory operations on a memory die while a current multi-level cell programming operation is being performed. In the event that a controller identifies pending memory operations to be performed in the memory die, the controller may communicate with the memory die to determine a status of auxiliary latches of the memory die. Depending on the status, the controller may determine if the memory die is in a suspend/resume period and/or which pending memory operations to have performed.

Abstract: A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for parity storage management. A system includes a plurality of storage elements. A system includes a controller that selects a parity storage element from a plurality of storage elements. A parity storage element has an error rate higher than other elements of a plurality of storage elements, and the parity storage element stores parity data for the plurality of storage elements.

Abstract: An electrostatic discharge protection circuit may include discharge path circuitry to discharge charge on a supply line in response to detection of an ESD event. The charge on the supply line may be discharged through the discharge path circuitry from when a first timing window opens until a second timing window closes. The first timing window may also be used to detect ESD events. The two timing windows may allow an initial period of the ESD voltage on the supply line to be suppressed before the second timing window opens, and may further allow a remaining period of the ESD event following the initial period to be suppressed after the first timing window closes.

Abstract: Systems and methods for controlling blocks in a memory device using a health indicator (such as the failed bit count) for the blocks are disclosed. However, the health indicator may exhibit noise, thereby resulting in an unreliable indicator of the health of the blocks in the memory device. In order to filter out the noise, a rolling average of the health indicator may be determined, and compared to the current health indicator. The comparison with the rolling average may indicate whether the current health indicator is an outlier, and thus should not be used. The health indicator may also be used to predict a future health indicator for different blocks in the memory device. Using the predicted future health indicator, the use of the blocks may be changed in order to more evenly wear the blocks.

Abstract: A method and system for using non-volatile memory as a replacement for volatile memory are provided. In one embodiment, a host is in communication with a memory system having volatile memory, a first non-volatile memory, and a second non-volatile memory, wherein the first non-volatile memory has a faster performance and a higher endurance than the second non-volatile memory. The host analyzes data to be stored in the volatile memory to determine if it should instead be stored in the first non-volatile memory. If the data should be stored in the volatile memory, the host stores the data in the volatile memory. If the data should be stored in the first non-volatile memory, the host stores the data in the first non-volatile memory.

Abstract: A circuit system may include a first stage circuit configured to generate two pairs of signals in response to an input signal. The circuit system may also include a second stage circuit that is configured to combine a first signal of a first pair with a first signal of a second pair to generate a first combined signal, and to combine a second signal of the first pair with a second signal of the second pair to generate a second combined signal. Transistors of the second stage circuit may be sized in relation to transition timings of the first and second pairs of signals such that skew and duty cycle distortion is minimized between the first and second combined signals.

Abstract: A system and method is disclosed for managing data in a garbage collection operation using a hybrid push-pull technique. The system includes multiple non-volatile memory sub-drives associated with a specific data type and shared volatile memory garbage collection buffer sized to only receive a predetermined amount of host data of a single data type and associated large data chunk correction data. A controller identifies and accumulates valid data of a single data type from the source block and combines it with XOR data for that valid data to generate a protected data stripe in the buffer. The controller writes the protected data stripe to the sub-drive containing data of the same data type. Only after writing the protected data stripe to the appropriate sub-drive, the controller repeats the process in the same source block for the same or different data type of data.

Abstract: A circuit may receive control signals to generate an output signal with pulses corresponding to pulses of a source signal. The circuit may include a primary circuit and an auxiliary circuit. The primary circuit may constantly participate in the generation of pulses of the output signal. The auxiliary circuit may selectively participate with the primary circuit in the generation of the pulses. For two consecutive pulses of the output signal, whether the auxiliary circuit participates in generating the latter of the two pulses may depend on whether a threshold level is crossed during generation of the consecutive pulses.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for memory array addressing. An addressing circuit is configured to receive an address for an operation on an array of multiple memory regions. An address includes a row address and a column address both multiplexed into the address and received with an activate command for an operation. A row buffer for an array of multiple memory regions is configured to store data identified by multiplexed row and column addresses from the multiple memory regions. Data of an operation is selected from a row buffer based on a second address received with a subsequent command for the operation.

Abstract: A system and method is disclosed for managing data in a garbage collection operation using a hybrid push-pull technique. The system includes multiple non-volatile memory sub-drives associated with a specific data type and shared volatile memory garbage collection buffer sized to only receive a predetermined amount of host data of a single data type and associated large data chunk correction data. A controller identifies and accumulates valid data of a single data type from the source block and combines it with XOR data for that valid data to generate a protected data stripe in the buffer. The controller writes the protected data stripe to the sub-drive containing data of the same data type. Only after writing the protected data stripe to the appropriate sub-drive, the controller repeats the process in the same source block for the same or different data type of data.