Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: Methods, systems, and computer readable media for submission queue pointer management are disclosed. One method is implemented in a data storage device including a controller and a memory. The method includes fetching a plurality of commands from a submission queue. The method further includes parsing at least one of the commands. The method further includes, in response to successful parsing of at least one of the commands and prior to executing all of the commands, notifying a host to advance a head entry pointer for the submission queue by a number of entries corresponding to a number of the commands successfully parsed.

Abstract: A temperature identification system may include temperature sensing circuitry and a temperature measurement module. The temperature sensing circuitry may include a ring oscillator that generates a ring oscillator output signal having a frequency that varies depending on an operating temperature on the ring oscillator. A frequency divider circuit may divide the frequency of the ring oscillator output signal such that two or more cycles of a noise component of supply voltage are averaged, which may reduce the impact that the noise has on the frequency of the ring oscillator output signal. In some embodiments, a regulator may supply a regulated voltage to the ring oscillator. The regulator may reduce the impact of the noise for low frequency components of the noise, while the frequency divider may reduce the impact for high frequency of the noise.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: A non-volatile memory system receives a request to read data. That request includes a quality of service indication. The memory system performs a read process that satisfies the quality of service indication and identifies a set of data with errors. The memory system returns the set of data with errors in response to the request.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

Abstract: The amount of remapping data in a file system of a memory device is reduced. In one aspect, for each request access, e.g., read or write operation, the memory cells of a primary physical address are evaluated. If the evaluation indicates the memory cells are good, the read or write operation proceeds. If the memory cells have a failure such as uncorrectable errors, the primary physical address is hashed to obtain an auxiliary physical address. If the auxiliary physical address is not available, the primary physical address can be hashed again to obtain another auxiliary physical address. In another aspect, per-page remapping is performed until a threshold number of bad pages in a block are detected, after which the entire block is remapped. In another aspect, pages of a block are remapped to auxiliary pages based on a block identifier.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for reduced routing signals. An apparatus includes a generator circuit that generates switch gate voltages for two or more word line switches. Two or more word line switches are on opposite sides of an array of memory elements and are for coupling word line voltages to word lines. An apparatus includes a word line switch circuit that supplies switch gate voltages to two or more word line switches. An apparatus includes a transistor control circuit that supplies select gate voltages to two or more select gates. Two or more select gates control select gate drain transistors. Select gate voltages are different from switch gate voltages. Select gate voltages and switch gate voltages are both based on a routing line voltage on a routing line that extends across an array of memory elements.

Abstract: Apparatuses, systems, and methods are disclosed for a chip with phase change memory (PCM) and magnetoresistive random access memory (MRAM). An apparatus includes a semiconductor circuit formed over a substrate of a chip. An apparatus includes a PCM array formed over a semiconductor circuit. An apparatus includes an MRAM array formed over a semiconductor circuit.

Abstract: This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.

Abstract: A data storage device includes an encoder and a memory that includes multiple storage elements. The encoder is configured to receive input data and to map at least one input group of bits of the input data to generate output data including at least one output group of bits. Each input group of bits of the at least one input group of bits and each output group of bits of the at least one output group of bits has the same number of bits. Each storage element of the multiple storage elements is configured to be programmed to a voltage state corresponding to an output group of bits of the at least one group of bits associated with the storage element.

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. The drain-end select gate transistors of unselected sub-blocks are made temporarily conductive for a time period during the ramp up of the unselected word line voltages to reduce the amount of capacitive coupling up of the respective memory string channel. This reduces a channel gradient which can exist in the memory string channels, thereby also reducing the read disturb. Further, the time period is greater when the selected word line is in a source-end or midrange subset of the word lines than when the selected word line is in a drain-end subset of the word lines. Another option involves omitting the injection disturb countermeasure, or providing a less severe injection disturb countermeasure, when the unselected sub-blocks are unprogrammed.

Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.

Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.

Abstract: A three-dimensional stacked memory device provides uniform programming speeds for a block of memory cells. The channel layers of the memory strings which are relatively close to a local interconnect of a stack are doped to account for a reduced blocking oxide thickness. Channel layers of remaining memory strings are undoped. The doping can be performing by masking the channel layers which are to remain undoped while exposing the other memory holes to a dopant. The dopant can be provided, e.g., in a carrier gas, spin on glass or other solid, or by plasma doping. An n-type dopant such as antimony, arsenic or phosphorus may be used. Heating causes the dopants to diffuse into the channel layer. Another approach deposits doped silicon for some of the channel layers and undoped silicon for other channel layers.